JAJSBT4D
August 2011 – April 2021
TPS53353
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings (1)
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
5-V LDO and VREG Start-Up
7.3.2
Adaptive On-Time D-CAP™ Control and Frequency Selection
7.3.3
Ramp Signal
7.3.4
Adaptive Zero Crossing
7.3.5
Power-Good
7.3.6
Current Sense, Overcurrent and Short Circuit Protection
7.3.7
Overvoltage and Undervoltage Protection
7.3.8
UVLO Protection
7.3.9
Thermal Shutdown
7.4
Device Functional Modes
7.4.1
Small Signal Model
7.4.2
Enable, Soft Start, and Mode Selection
7.4.3
Auto-Skip Eco-mode™ Light Load Operation
7.4.4
Forced Continuous Conduction Mode
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Typical Application Circuit Diagram
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
External Component Selection
8.2.1.3
Application Curves
8.2.2
Typical Application Circuit Diagram With Ceramic Output Capacitors
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.2.1
External Component Selection
8.2.2.2.2
External Component Selection Using All Ceramic Output Capacitors
8.2.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.2
Receiving Notification of Documentation Updates
11.3
サポート・リソース
11.4
Trademarks
11.5
静電気放電に関する注意事項
11.6
用語集
2
アプリケーション
エンタープライズ・ラック・サーバー
および
ストレージ
有線ネットワーク・スイッチ
および
ルータ
ASIC、SoC、
FPGA
、DSP コア、I/O 電圧