JAJSC96C October   2013  – September 2016 TPS7B4250-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Regulated Output (VOUT)
      2. 7.3.2 Undervoltage Shutdown
      3. 7.3.3 Thermal Protection
      4. 7.3.4 VOUT Short to Battery
      5. 7.3.5 Tracking Regulator with ENABLE Circuit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VI < 4 V
      2. 7.4.2 Operation With ADJ/EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Mounting
      2. 10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation and Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

10 Layout

10.1 Layout Guidelines

10.1.1 Package Mounting

Solder-pad footprint recommendations for the TPS7B4250-Q1 device are available in the メカニカル、パッケージ、および注文情報 section and at www.ti.com.

10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance

To improve AC performance such as PSRR, output noise, and transient response, TI recommends to design the board with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of the device.

Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure stability. Every capacitor must be placed as close as possible to the device and on the same side of the PCB as the regulator.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because of the negative impact on system performance. Vias and long traces can also cause instability.

If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout pattern used for TPS7B4250 evaluation board, available at www.ti.com.

10.2 Layout Example

TPS7B4250-Q1 layout_slvsca0.gif Figure 19. TPS7B4250-Q1 Layout Example

10.3 Power Dissipation and Thermal Considerations

Device power dissipation is calculated with Equation 1.

Equation 1. TPS7B4250-Q1 eq_3_dissipation_slvsca0.gif

where

  • PD = continuous power dissipation
  • IO = output current
  • VI = input voltage
  • VO = output voltage
  • IQ = quiescent current

As IQ « IO, the term IQ × VI in Equation 1 can be ignored.

For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ) with Equation 2.

Equation 2. TPS7B4250-Q1 eq_4_tj_slvsca0.gif

where

  • θJA = junction-to-junction-ambient air thermal impedance

A rise in junction temperature because of power dissipation can be calculated with Equation 3.

Equation 3. TPS7B4250-Q1 eq_5_delta_tj_slvsca0.gif

For a given maximum junction temperature (TJM), the maximum ambient air temperature (TAM) at which the device can operate can be calculated with Equation 4.

Equation 4. TPS7B4250-Q1 eq_6_max_ta_slvsca0.gif