JAJSCC4A July 2016 – January 2024 DS90UB964-Q1
PRODUCTION DATA
Table 5-148 lists the memory-mapped registers for the PATGEN_And_CSI-2 registers. All register offset addresses not listed in Table 5-148 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
0x1 | PGEN_CTL | PGEN_CTL | Go |
0x2 | PGEN_CFG | PGEN_CFG | Go |
0x3 | PGEN_CSI_DI | PGEN_CSI_DI | Go |
0x4 | PGEN_LINE_SIZE1 | PGEN_LINE_SIZE1 | Go |
0x5 | PGEN_LINE_SIZE0 | PGEN_LINE_SIZE0 | Go |
0x6 | PGEN_BAR_SIZE1 | PGEN_BAR_SIZE1 | Go |
0x7 | PGEN_BAR_SIZE0 | PGEN_BAR_SIZE0 | Go |
0x8 | PGEN_ACT_LPF1 | PGEN_ACT_LPF1 | Go |
0x9 | PGEN_ACT_LPF0 | PGEN_ACT_LPF0 | Go |
0xA | PGEN_TOT_LPF1 | PGEN_TOT_LPF1 | Go |
0xB | PGEN_TOT_LPF0 | PGEN_TOT_LPF0 | Go |
0xC | PGEN_LINE_PD1 | PGEN_LINE_PD1 | Go |
0xD | PGEN_LINE_PD0 | PGEN_LINE_PD0 | Go |
0xE | PGEN_VBP | PGEN_VBP | Go |
0xF | PGEN_VFP | PGEN_VFP | Go |
0x10 | PGEN_COLOR0 | PGEN_COLOR0 | Go |
0x11 | PGEN_COLOR1 | PGEN_COLOR1 | Go |
0x12 | PGEN_COLOR2 | PGEN_COLOR2 | Go |
0x13 | PGEN_COLOR3 | PGEN_COLOR3 | Go |
0x14 | PGEN_COLOR4 | PGEN_COLOR4 | Go |
0x15 | PGEN_COLOR5 | PGEN_COLOR5 | Go |
0x16 | PGEN_COLOR6 | PGEN_COLOR6 | Go |
0x17 | PGEN_COLOR7 | PGEN_COLOR7 | Go |
0x18 | PGEN_COLOR8 | PGEN_COLOR8 | Go |
0x19 | PGEN_COLOR9 | PGEN_COLOR9 | Go |
0x1A | PGEN_COLOR10 | PGEN_COLOR10 | Go |
0x1B | PGEN_COLOR11 | PGEN_COLOR11 | Go |
0x1C | PGEN_COLOR12 | PGEN_COLOR12 | Go |
0x1D | PGEN_COLOR13 | PGEN_COLOR13 | Go |
0x1E | PGEN_COLOR14 | PGEN_COLOR14 | Go |
0x40 | CSI0_TCK_PREP | CSI0_TCK_PREP | Go |
0x41 | CSI0_TCK_ZERO | CSI0_TCK_ZERO | Go |
0x42 | CSI0_TCK_TRAIL | CSI0_TCK_TRAIL | Go |
0x43 | CSI0_TCK_POST | CSI0_TCK_POST | Go |
0x44 | CSI0_THS_PREP | CSI0_THS_PREP | Go |
0x45 | CSI0_THS_ZERO | CSI0_THS_ZERO | Go |
0x46 | CSI0_THS_TRAIL | CSI0_THS_TRAIL | Go |
0x47 | CSI0_THS_EXIT | CSI0_THS_EXIT | Go |
0x48 | CSI0_TPLX | CSI0_TPLX | Go |
0x60 | CSI1_TCK_PREP | CSI1_TCK_PREP | Go |
0x61 | CSI1_TCK_ZERO | CSI1_TCK_ZERO | Go |
0x62 | CSI1_TCK_TRAIL | CSI1_TCK_TRAIL | Go |
0x63 | CSI1_TCK_POST | CSI1_TCK_POST | Go |
0x64 | CSI1_THS_PREP | CSI1_THS_PREP | Go |
0x65 | CSI1_THS_ZERO | CSI1_THS_ZERO | Go |
0x66 | CSI1_THS_TRAIL | CSI1_THS_TRAIL | Go |
0x67 | CSI1_THS_EXIT | CSI1_THS_EXIT | Go |
0x68 | CSI1_TPLX | CSI1_TPLX | Go |
Complex bit access types are encoded to fit into small table cells. Table 5-149 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
PGEN_CTL is shown in Table 5-150.
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Pattern Generator Control Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | RESERVED | R | 0x0 | Reserved |
0 | PGEN_ENABLE | R/W | 0x0 | Pattern Generator Enable 1: Enable Pattern Generator 0: Disable Pattern Generator |
PGEN_CFG is shown in Table 5-151.
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Pattern Generator Configuration Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | PGEN_FIXED_EN | R/W | 0x0 | Fixed Pattern Enable Setting this bit enables Fixed Color Patterns. 0: Send Color Bar Pattern 1: Send Fixed Color Pattern |
6 | RESERVED | R | 0x0 | Reserved |
5:4 | NUM_CBARS | R/W | 0x3 | Number of Color Bars 00: 1 Color Bar 01: 2 Color Bars 10: 4 Color Bars 11: 8 Color Bars |
3:0 | BLOCK_SIZE | R/W | 0x3 | Block Size. For Fixed Color Patterns, this field controls the size of the fixed color field in bytes. Allowed values are 1 to 15. |
PGEN_CSI_DI is shown in Table 5-152.
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Pattern Generator CSI DI Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | PGEN_CSI_VC | R/W | 0x0 | CSI Virtual Channel Identifier This field controls the value sent in the CSI packet for the Virtual Channel Identifier |
5:0 | PGEN_CSI_DT | R/W | 0x24 | CSI Data Type This field controls the value sent in the CSI packet for the Data Type. The default value (0x24) indicates RGB888. |
PGEN_LINE_SIZE1 is shown in Table 5-153.
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Pattern Generator Line Size Register 1
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_LINE_SIZE[15:8] | R/W | 0x7 | Most significant byte of the Pattern Generator line size. This is the active line length in bytes. Default setting is for 1920 bytes for a 640 pixel line width. |
PGEN_LINE_SIZE0 is shown in Table 5-154.
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Pattern Generator Line Size Register 0
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_LINE_SIZE[7:0] | R/W | 0x80 | Least significant byte of the Pattern Generator line size. This is the active line length in bytes. Default setting is for 1920 bytes for a 640 pixel line width. |
PGEN_BAR_SIZE1 is shown in Table 5-155.
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Pattern Generator Bar Size Register 1
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_BAR_SIZE[15:8] | R/W | 0x0 | Most significant byte of the Pattern Generator color bar size. This is the active length in bytes for the color bars. This value is used for all except the last color bar. The last color bar is determined by the remaining bytes as defined by the PGEN_LINE_SIZE value. |
PGEN_BAR_SIZE0 is shown in Table 5-156.
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Pattern Generator Bar Size Register 0
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_BAR_SIZE[7:0] | R/W | 0xF0 | Least significant byte of the Pattern Generator color bar size. This is the active length in bytes for the color bars. This value is used for all except the last color bar. The last color bar is determined by the remaining bytes as defined by the PGEN_LINE_SIZE value. |
PGEN_ACT_LPF1 is shown in Table 5-157.
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Pattern Generator Active LPF Register 1
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_ACT_LPF[15:8] | R/W | 0x1 | Active Lines Per Frame Most significant byte of the number of active lines per frame. Default setting is for 480 active lines per frame. |
PGEN_ACT_LPF0 is shown in Table 5-158.
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Pattern Generator Active LPF Register 0
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_ACT_LPF[7:0] | R/W | 0xE0 | Active Lines Per Frame Least significant byte of the number of active lines per frame. Default setting is for 480 active lines per frame. |
PGEN_TOT_LPF1 is shown in Table 5-159.
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Pattern Generator Total LPF Register 1
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_TOT_LPF[15:8] | R/W | 0x2 | Total Lines Per Frame Most significant byte of the number of total lines per frame including vertical blanking |
PGEN_TOT_LPF0 is shown in Table 5-160.
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Pattern Generator Total LPF Register 0
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_TOT_LPF[7:0] | R/W | 0xD | Total Lines Per Frame Least significant byte of the number of total lines per frame including vertical blanking |
PGEN_LINE_PD1 is shown in Table 5-161.
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Pattern Generator Line Period Register 1
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_LINE_PD[15:8] | R/W | 0xC | Line Period Most significant byte of the line period in 10ns units. The default setting for the line period registers sets a line period of 31.75 microseconds. |
PGEN_LINE_PD0 is shown in Table 5-162.
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Pattern Generator Line Period Register 0
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_LINE_PD[7:0] | R/W | 0x67 | Line Period Least significant byte of the line period in 10ns units. The default setting for the line period registers sets a line period of 31.75 microseconds. |
PGEN_VBP is shown in Table 5-163.
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Pattern Generator VBP Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_VBP | R/W | 0x21 | Vertical Back Porch This value provides the vertical back porch portion of the vertical blanking interval. This value provides the number of blank lines between the FrameStart packet and the first video data packet. |
PGEN_VFP is shown in Table 5-164.
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Pattern Generator VFP Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_VFP | R/W | 0xA | Vertical Front Porch This value provides the vertical front porch portion of the vertical blanking interval. This value provides the number of blank lines between the last video line and the FrameEnd packet. |
PGEN_COLOR0 is shown in Table 5-165.
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Pattern Generator Color 0 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR0 | R/W | 0xAA | Pattern Generator Color 0 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 0. For Fixed Color Patterns, this register controls the first byte of the fixed color pattern. |
PGEN_COLOR1 is shown in Table 5-166.
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Pattern Generator Color 1 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR1 | R/W | 0x33 | Pattern Generator Color 1 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 1. For Fixed Color Patterns, this register controls the second byte of the fixed color pattern. |
PGEN_COLOR2 is shown in Table 5-167.
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Pattern Generator Color 2 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR2 | R/W | 0xF0 | Pattern Generator Color 2 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 2. For Fixed Color Patterns, this register controls the third byte of the fixed color pattern. |
PGEN_COLOR3 is shown in Table 5-168.
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Pattern Generator Color 3 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR3 | R/W | 0x7F | Pattern Generator Color 3 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 3. For Fixed Color Patterns, this register controls the fourth byte of the fixed color pattern. |
PGEN_COLOR4 is shown in Table 5-169.
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Pattern Generator Color 4 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR4 | R/W | 0x55 | Pattern Generator Color 4 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 4. For Fixed Color Patterns, this register controls the fifth byte of the fixed color pattern. |
PGEN_COLOR5 is shown in Table 5-170.
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Pattern Generator Color 5 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR5 | R/W | 0xCC | Pattern Generator Color 5 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 5. For Fixed Color Patterns, this register controls the sixth byte of the fixed color pattern. |
PGEN_COLOR6 is shown in Table 5-171.
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Pattern Generator Color 6 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR6 | R/W | 0xF | Pattern Generator Color 6 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 6. For Fixed Color Patterns, this register controls the seventh byte of the fixed color pattern. |
PGEN_COLOR7 is shown in Table 5-172.
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Pattern Generator Color 7 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR7 | R/W | 0x80 | Pattern Generator Color 7 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 7. For Fixed Color Patterns, this register controls the eighth byte of the fixed color pattern. |
PGEN_COLOR8 is shown in Table 5-173.
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Pattern Generator Color 8 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR8 | R/W | 0x0 | Pattern Generator Color 8 For Fixed Color Patterns, this register controls the ninth byte of the fixed color pattern. |
PGEN_COLOR9 is shown in Table 5-174.
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Pattern Generator Color 9 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR9 | R/W | 0x0 | Pattern Generator Color 9 For Fixed Color Patterns, this register controls the tenth byte of the fixed color pattern. |
PGEN_COLOR10 is shown in Table 5-175.
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Pattern Generator Color 10 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR10 | R/W | 0x0 | Pattern Generator Color 10 For Fixed Color Patterns, this register controls the eleventh byte of the fixed color pattern. |
PGEN_COLOR11 is shown in Table 5-176.
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Pattern Generator Color 11 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR11 | R/W | 0x0 | Pattern Generator Color 11 For Fixed Color Patterns, this register controls the twelfth byte of the fixed color pattern. |
PGEN_COLOR12 is shown in Table 5-177.
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Pattern Generator Color 12 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR12 | R/W | 0x0 | Pattern Generator Color 12 For Fixed Color Patterns, this register controls the thirteenth byte of the fixed color pattern. |
PGEN_COLOR13 is shown in Table 5-178.
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Pattern Generator Color 13 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR13 | R/W | 0x0 | Pattern Generator Color 13 For Fixed Color Patterns, this register controls the fourteenth byte of the fixed color pattern. |
PGEN_COLOR14 is shown in Table 5-179.
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Pattern Generator Color 14 Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PGEN_COLOR14 | R/W | 0x0 | Pattern Generator Color 14 For Fixed Color Patterns, this register controls the fifteenth byte of the fixed color pattern. |
CSI0_TCK_PREP is shown in Table 5-180.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_TCK_PREP_OV | R/W | 0x0 | Override CSI Tck-prep parameter 0: Tck-prep is automatically determined 1: Override Tck-prep with value in bits 6:0 of this register |
6:0 | MR_TCK_PREP | R/W | 0x0 | Tck-prep value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI0_TCK_ZERO is shown in Table 5-181.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_TCK_ZERO_OV | R/W | 0x0 | Override CSI Tck-zero parameter 0: Tck-zero is automatically determined 1: Override Tck-zero with value in bits 6:0 of this register |
6:0 | MR_TCK_ZERO | R/W | 0x0 | Tck-zero value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI0_TCK_TRAIL is shown in Table 5-182.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_TCK_TRAIL_OV | R/W | 0x0 | Override CSI Tck-trail parameter 0: Tck-trail is automatically determined 1: Override Tck-trail with value in bits 6:0 of this register |
6:0 | MR_TCK_TRAIL | R/W | 0x0 | Tck-trail value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI0_TCK_POST is shown in Table 5-183.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_TCK_POST_OV | R/W | 0x0 | Override CSI Tck-post parameter 0: Tck-post is automatically determined 1: Override Tck-post with value in bits 6:0 of this register |
6:0 | MR_TCK_POST | R/W | 0x0 | Tck-post value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI0_THS_PREP is shown in Table 5-184.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_THS_PREP_OV | R/W | 0x0 | Override CSI Ths-prep parameter 0: Ths-prep is automatically determined 1: Override Ths-prep with value in bits 6:0 of this register |
6:0 | MR_THS_PREP | R/W | 0x0 | Ths-prep value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI0_THS_ZERO is shown in Table 5-185.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_THS_ZERO_OV | R/W | 0x0 | Override CSI Ths-zero parameter 0: Ths-zero is automatically determined 1: Override Ths-zero with value in bits 6:0 of this register |
6:0 | MR_THS_ZERO | R/W | 0x0 | Ths-zero value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI0_THS_TRAIL is shown in Table 5-186.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_THS_TRAIL_OV | R/W | 0x0 | Override CSI Ths-trail parameter 0: Ths-trail is automatically determined 1: Override Ths-trail with value in bits 6:0 of this register |
6:0 | MR_THS_TRAIL | R/W | 0x0 | Ths-trail value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI0_THS_EXIT is shown in Table 5-187.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_THS_EXIT_OV | R/W | 0x0 | Override CSI Ths-exit parameter 0: Ths-exit is automatically determined 1: Override Ths-exit with value in bits 6:0 of this register |
6:0 | MR_THS_EXIT | R/W | 0x0 | Ths-exit value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI0_TPLX is shown in Table 5-188.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_TPLX_OV | R/W | 0x0 | Override CSI Tplx parameter 0: Tplx is automatically determined 1: Override Tplx with value in bits 6:0 of this register |
6:0 | MR_TPLX | R/W | 0x0 | Tplx value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI1_TCK_PREP is shown in Table 5-189.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_TCK_PREP_OV | R/W | 0x0 | Override CSI Tck-prep parameter 0: Tck-prep is automatically determined 1: Override Tck-prep with value in bits 6:0 of this register |
6:0 | MR_TCK_PREP | R/W | 0x0 | Tck-prep value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI1_TCK_ZERO is shown in Table 5-190.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_TCK_ZERO_OV | R/W | 0x0 | Override CSI Tck-zero parameter 0: Tck-zero is automatically determined 1: Override Tck-zero with value in bits 6:0 of this register |
6:0 | MR_TCK_ZERO | R/W | 0x0 | Tck-zero value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI1_TCK_TRAIL is shown in Table 5-191.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_TCK_TRAIL_OV | R/W | 0x0 | Override CSI Tck-trail parameter 0: Tck-trail is automatically determined 1: Override Tck-trail with value in bits 6:0 of this register |
6:0 | MR_TCK_TRAIL | R/W | 0x0 | Tck-trail value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI1_TCK_POST is shown in Table 5-192.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_TCK_POST_OV | R/W | 0x0 | Override CSI Tck-post parameter 0: Tck-post is automatically determined 1: Override Tck-post with value in bits 6:0 of this register |
6:0 | MR_TCK_POST | R/W | 0x0 | Tck-post value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI1_THS_PREP is shown in Table 5-193.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_THS_PREP_OV | R/W | 0x0 | Override CSI Ths-prep parameter 0: Ths-prep is automatically determined 1: Override Ths-prep with value in bits 6:0 of this register |
6:0 | MR_THS_PREP | R/W | 0x0 | Ths-prep value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI1_THS_ZERO is shown in Table 5-194.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_THS_ZERO_OV | R/W | 0x0 | Override CSI Ths-zero parameter 0: Ths-zero is automatically determined 1: Override Ths-zero with value in bits 6:0 of this register |
6:0 | MR_THS_ZERO | R/W | 0x0 | Ths-zero value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI1_THS_TRAIL is shown in Table 5-195.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_THS_TRAIL_OV | R/W | 0x0 | Override CSI Ths-trail parameter 0: Ths-trail is automatically determined 1: Override Ths-trail with value in bits 6:0 of this register |
6:0 | MR_THS_TRAIL | R/W | 0x0 | Ths-trail value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI1_THS_EXIT is shown in Table 5-196.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_THS_EXIT_OV | R/W | 0x0 | Override CSI Ths-exit parameter 0: Ths-exit is automatically determined 1: Override Ths-exit with value in bits 6:0 of this register |
6:0 | MR_THS_EXIT | R/W | 0x0 | Ths-exit value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |
CSI1_TPLX is shown in Table 5-197.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | MR_TPLX_OV | R/W | 0x0 | Override CSI Tplx parameter 0: Tplx is automatically determined 1: Override Tplx with value in bits 6:0 of this register |
6:0 | MR_TPLX | R/W | 0x0 | Tplx value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. If bit 7 of this register is 1, this field is read/write. |