JAJSCC4A July 2016 – January 2024 DS90UB964-Q1
PRODUCTION DATA
Table 5-16 lists the memory-mapped registers for the Main_Page registers. All register offset addresses not listed in Table 5-16 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
0x0 | I2C_DEVICE_ID | I2C_DEVICE_ID | Go |
0x1 | RESET_CTL | RESET_CTL | Go |
0x2 | GENERAL_CFG | GENERAL_CFG | Go |
0x3 | REV_MASK_ID | REV_MASK_ID | Go |
0x4 | DEVICE_STS | DEVICE_STS | Go |
0x5 | PAR_ERR_THOLD1 | PAR_ERR_THOLD1 | Go |
0x6 | PAR_ERR_THOLD0 | PAR_ERR_THOLD0 | Go |
0x7 | BCC_WATCHDOG_CONTROL | BCC_WATCHDOG_CONTROL | Go |
0x8 | I2C_CONTROL_1 | I2C_CONTROL_1 | Go |
0x9 | I2C_CONTROL_2 | I2C_CONTROL_2 | Go |
0xA | SCL_HIGH_TIME | SCL_HIGH_TIME | Go |
0xB | SCL_LOW_TIME | SCL_LOW_TIME | Go |
0xC | RX_PORT_CTL | RX_PORT_CTL | Go |
0xD | IO_CTL | IO_CTL | Go |
0xE | GPIO_PIN_STS | GPIO_PIN_STS | Go |
0xF | GPIO_INPUT_CTL | GPIO_INPUT_CTL | Go |
0x10 | GPIO0_PIN_CTL | GPIO0_PIN_CTL | Go |
0x11 | GPIO1_PIN_CTL | GPIO1_PIN_CTL | Go |
0x12 | GPIO2_PIN_CTL | GPIO2_PIN_CTL | Go |
0x13 | GPIO3_PIN_CTL | GPIO3_PIN_CTL | Go |
0x14 | GPIO4_PIN_CTL | GPIO4_PIN_CTL | Go |
0x15 | GPIO5_PIN_CTL | GPIO5_PIN_CTL | Go |
0x16 | GPIO6_PIN_CTL | GPIO6_PIN_CTL | Go |
0x17 | GPIO7_PIN_CTL | GPIO7_PIN_CTL | Go |
0x18 | FS_CTL | FS_CTL | Go |
0x19 | FS_HIGH_TIME_1 | FS_HIGH_TIME_1 | Go |
0x1A | FS_HIGH_TIME_0 | FS_HIGH_TIME_0 | Go |
0x1B | FS_LOW_TIME_1 | FS_LOW_TIME_1 | Go |
0x1C | FS_LOW_TIME_0 | FS_LOW_TIME_0 | Go |
0x1D | MAX_FRM_HI | MAX_FRM_HI | Go |
0x1E | MAX_FRM_LO | MAX_FRM_LO | Go |
0x1F | CSI_PLL_CTL | CSI_PLL_CTL | Go |
0x20 | FWD_CTL1 | FWD_CTL1 | Go |
0x21 | FWD_CTL2 | FWD_CTL2 | Go |
0x22 | FWD_STS | FWD_STS | Go |
0x23 | INTERRUPT_CTL | INTERRUPT_CTL | Go |
0x24 | INTERRUPT_STS | INTERRUPT_STS | Go |
0x25 | TS_CONFIG | TS_CONFIG | Go |
0x26 | TS_CONTROL | TS_CONTROL | Go |
0x27 | TS_LINE_HI | TS_LINE_HI | Go |
0x28 | TS_LINE_LO | TS_LINE_LO | Go |
0x29 | TS_STATUS | TS_STATUS | Go |
0x2A | TIMESTAMP_P0_HI | TIMESTAMP_P0_HI | Go |
0x2B | TIMESTAMP_P0_LO | TIMESTAMP_P0_LO | Go |
0x2C | TIMESTAMP_P1_HI | TIMESTAMP_P1_HI | Go |
0x2D | TIMESTAMP_P1_LO | TIMESTAMP_P1_LO | Go |
0x2E | TIMESTAMP_P2_HI | TIMESTAMP_P2_HI | Go |
0x2F | TIMESTAMP_P2_LO | TIMESTAMP_P2_LO | Go |
0x30 | TIMESTAMP_P3_HI | TIMESTAMP_P3_HI | Go |
0x31 | TIMESTAMP_P3_LO | TIMESTAMP_P3_LO | Go |
0x32 | CSI_PORT_SEL | CSI_PORT_SEL | Go |
0x33 | CSI_CTL | CSI_CTL | Go |
0x34 | CSI_CTL2 | CSI_CTL2 | Go |
0x35 | CSI_STS | CSI_STS | Go |
0x36 | CSI_TX_ICR | CSI_TX_ICR | Go |
0x37 | CSI_TX_ISR | CSI_TX_ISR | Go |
0x41 | SFILTER_CFG | SFILTER_CFG | Go |
0x42 | AEQ_CTL | AEQ_CTL | Go |
0x43 | AEQ_ERR_THOLD | AEQ_ERR_THOLD | Go |
0x4C | FPD3_PORT_SEL | FPD3_PORT_SEL | Go |
0x4D | RX_PORT_STS1 | RX_PORT_STS1 | Go |
0x4E | RX_PORT_STS2 | RX_PORT_STS2 | Go |
0x4F | RX_FREQ_HIGH | RX_FREQ_HIGH | Go |
0x50 | RX_FREQ_LOW | RX_FREQ_LOW | Go |
0x55 | RX_PAR_ERR_HI | RX_PAR_ERR_HI | Go |
0x56 | RX_PAR_ERR_LO | RX_PAR_ERR_LO | Go |
0x57 | BIST_ERR_COUNT | BIST_ERR_COUNT | Go |
0x58 | BCC_CONFIG | BCC_CONFIG | Go |
0x59 | DATAPATH_CTL1 | DATAPATH_CTL1 | Go |
0x5A | DATAPATH_CTL2 | DATAPATH_CTL2 | Go |
0x5B | SER_ID | SER_ID | Go |
0x5C | SER_ALIAS_ID | SER_ALIAS_ID | Go |
0x5D | TARGET_ID_0 | TARGET_ID_0 | Go |
0x5E | TARGET_ID_1 | TARGET_ID_1 | Go |
0x5F | TARGET_ID_2 | TARGET_ID_2 | Go |
0x60 | TARGET_ID_3 | TARGET_ID_3 | Go |
0x61 | TARGET_ID_4 | TARGET_ID_4 | Go |
0x62 | TARGET_ID_5 | TARGET_ID_5 | Go |
0x63 | TARGET_ID_6 | TARGET_ID_6 | Go |
0x64 | TARGET_ID_7 | TARGET_ID_7 | Go |
0x65 | TARGET_ALIAS_0 | TARGET_ALIAS_0 | Go |
0x66 | TARGET_ALIAS_1 | TARGET_ALIAS_1 | Go |
0x67 | TARGET_ALIAS_2 | TARGET_ALIAS_2 | Go |
0x68 | TARGET_ALIAS_3 | TARGET_ALIAS_3 | Go |
0x69 | TARGET_ALIAS_4 | TARGET_ALIAS_4 | Go |
0x6A | TARGET_ALIAS_5 | TARGET_ALIAS_5 | Go |
0x6B | TARGET_ALIAS_6 | TARGET_ALIAS_6 | Go |
0x6C | TARGET_ALIAS_7 | TARGET_ALIAS_7 | Go |
0x6D | PORT_CONFIG | PORT_CONFIG | Go |
0x6E | BC_GPIO_CTL0 | BC_GPIO_CTL0 | Go |
0x6F | BC_GPIO_CTL1 | BC_GPIO_CTL1 | Go |
0x70 | RAW10_ID | RAW10_ID | Go |
0x71 | RAW12_ID | RAW12_ID | Go |
0x73 | LINE_COUNT_1 | LINE_COUNT_1 | Go |
0x74 | LINE_COUNT_0 | LINE_COUNT_0 | Go |
0x75 | LINE_LEN_1 | LINE_LEN_1 | Go |
0x76 | LINE_LEN_0 | LINE_LEN_0 | Go |
0x77 | FREQ_DET_CTL | FREQ_DET_CTL | Go |
0x78 | MAILBOX_1 | MAILBOX_1 | Go |
0x79 | MAILBOX_2 | MAILBOX_2 | Go |
0x7C | PORT_CONFIG2 | PORT_CONFIG2 | Go |
0x7D | PORT_PASS_CTL | PORT_PASS_CTL | Go |
0xB0 | IND_ACC_CTL | IND_ACC_CTL | Go |
0xB1 | IND_ACC_ADDR | IND_ACC_ADDR | Go |
0xB2 | IND_ACC_DATA | IND_ACC_DATA | Go |
0xB3 | BIST_CTL | BIST_CTL | Go |
0xB6 | PAR_ERR_CTRL | PAR_ERR_CTRL | Go |
0xB8 | MODE_IDX_STS | MODE_IDX_STS | Go |
0xB9 | LINK_ERROR_COUNT | LINK_ERROR_COUNT | Go |
0xBC | FV_MIN_TIME | FV_MIN_TIME | Go |
0xBE | GPIO_PD_CTL | GPIO_PD_CTL | Go |
0xD0 | PORT_DEBUG | PORT_DEBUG | Go |
0xD2 | AEQ_CTL2 | AEQ_CTL2 | Go |
0xD3 | AEQ_STATUS | AEQ_STATUS | Go |
0xD4 | AEQ_BYPASS | AEQ_BYPASS | Go |
0xD5 | AEQ_MIN_MAX | AEQ_MIN_MAX | Go |
0xD8 | PORT_ICR_HI | PORT_ICR_HI | Go |
0xD9 | PORT_ICR_LO | PORT_ICR_LO | Go |
0xDA | PORT_ISR_HI | PORT_ISR_HI | Go |
0xDB | PORT_ISR_LO | PORT_ISR_LO | Go |
0xF0 | FPD3_RX_ID0 | FPD3_RX_ID0 | Go |
0xF1 | FPD3_RX_ID1 | FPD3_RX_ID1 | Go |
0xF2 | FPD3_RX_ID2 | FPD3_RX_ID2 | Go |
0xF3 | FPD3_RX_ID3 | FPD3_RX_ID3 | Go |
0xF4 | FPD3_RX_ID4 | FPD3_RX_ID4 | Go |
0xF5 | FPD3_RX_ID5 | FPD3_RX_ID5 | Go |
0xF8 | I2C_RX0_ID | I2C_RX0_ID | Go |
0xF9 | I2C_RX1_ID | I2C_RX1_ID | Go |
0xFA | I2C_RX2_ID | I2C_RX2_ID | Go |
0xFB | I2C_RX3_ID | I2C_RX3_ID | Go |
Complex bit access types are encoded to fit into small table cells. Table 5-17 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RC | R C | Read to Clear |
RH | R H | Read Set or cleared by hardware |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value |
I2C_DEVICE_ID is shown in Table 5-18.
Return to the Summary Table.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | DEVICE_ID | R/W | 0x0 | 7-bit I2C ID of Deserializer. This field always indicates the current value of the I2C ID. When bit 0 of this register is 0, this field is read-only and show the strapped ID. When bit 1 of this register is 1, this field is read/write and can be used to assign any valid I2C ID. |
0 | DES_ID | R/W | 0x0 | 0: Device ID is from strap 1: Register I2C Device ID overrides strapped value |
RESET_CTL is shown in Table 5-19.
Return to the Summary Table.
Reset control register This register can only be written from the primary local I2C interface.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0x0 | Reserved |
5 | RESERVED | R | 0x0 | Reserved |
4:3 | RESERVED | R | 0x0 | Reserved |
2 | RESTART_AUTOLOAD | RH/W1S | 0x0 | Restart ROM Auto-load Setting this bit to 1 causes a re-load of the ROM. This bit is self-clearing. Software can check for Auto-load complete by checking the CFG_INIT_DONE bit in the DEVICE_STS register. |
1 | DIGITAL_RESET1 | RH/W1S | 0x0 | Digital Reset Resets the entire digital block including registers. This bit is self-clearing. 1: Reset 0: Normal operation |
0 | DIGITAL_RESET0 | RH/W1S | 0x0 | Digital Reset Resets the entire digital block except registers. This bit is self-clearing. 1: Reset 0: Normal operation |
GENERAL_CFG is shown in Table 5-20.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0x0 | Reserved |
4 | OUTPUT_EN_MODE | R/W | 0x1 | Output Enable Mode If set to 0, the CSI TX output port is forced to the high-impedance state if no assigned RX ports have an active Receiver lock. If set to 1, the CSI TX output port continues in normal operation if no assigned RX ports have an active Receiver lock. CSI TX operation remains under register control via the CSI_CTL register for each port. If no assigned RX ports have an active Receiver lock, this results in the CSI Transmitter entering the LP-11 state. |
3 | OUTPUT_ENABLE | R/W | 0x1 | Output Enable Control (in conjunction with Output Sleep State Select) If OUTPUT_SLEEP_STATE_SEL is set to 1 and this bit is set to 0, the CSI TX outputs are forced into a high impedance state. |
2 | OUTPUT_SLEEP_STATE_SEL | R/W | 0x1 | OSS Select to control output state when LOCK is low (used in conjunction with Output Enable) When this bit is set to 0, the CSI TX outputs are forced into a HS-0 state. |
1 | RX_PARITY_CHECK_EN | R/W | 0x1 | FPD3 Receiver Parity Checker Enable When enabled, the parity check function is enabled for the FPD3 receiver. This allows detection of errors on the FPD3 receiver data bits. 0: Disable 1: Enable |
0 | FORCE_REFCLK_DET | R/W | 0x0 | Force indication of external reference clock 0: Normal operation, reference clock detect circuit indicates the presence of an external reference clock 1: Force reference clock to be indicated present |
REV_MASK_ID is shown in Table 5-21.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:4 | REVISION_ID | R | 0x0 | Revision ID 0010: DS90UB964 A0 0011: DS90UB964 A1 |
3:0 | MASK_ID | R | 0x0 | Mask ID |
DEVICE_STS is shown in Table 5-22.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | CFG_CKSUM_STS | R | 0x1 | Config Checksum Passed This bit is set following initialization if the Configuration data in the eFuse ROM had a valid checksum |
6 | CFG_INIT_DONE | R | 0x1 | Power-up initialization complete This bit is set after Initialization is complete. Configuration from eFuse ROM has completed. |
5:2 | RESERVED | R | 0x0 | Reserved |
1 | RESERVED | R | 0x0 | Reserved |
0 | RESERVED | R | 0x0 | Reserved |
PAR_ERR_THOLD1 is shown in Table 5-23.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PAR_ERR_THOLD_HI | R/W | 0x1 | FPD3 Parity Error Threshold High byte This register provides the 8 most significant bits of the Parity Error Threshold value. For each port, if the FPD-Link III receiver detects a number of parity errors greater than or equal to this value, the PARITY_ERROR flag is set in the RX_PORT_STS1 register. |
PAR_ERR_THOLD0 is shown in Table 5-24.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PAR_ERR_THOLD_LO | R/W | 0x0 | FPD3 Parity Error Threshold Low byte This register provides the 8 least significant bits of the Parity Error Threshold value. For each port, if the FPD-Link III receiver detects a number of parity errors greater than or equal to this value, the PARITY_ERROR flag is set in the RX_PORT_STS1 register. |
BCC_WATCHDOG_CONTROL is shown in Table 5-25.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | BCC_WATCHDOG_TIMER | R/W | 0x7F | The watchdog timer allows termination of a control channel transaction if the transaction fails to complete within a programmed amount of time. This field sets the Bidirectional Control Channel Watchdog Timeout value in units of 2 milliseconds. This field must not be set to 0. |
0 | BCC_WATCHDOG_TIMER_DISABLE | R/W | 0x0 | Disable Bidirectional Control Channel Watchdog Timer 1: Disables BCC Watchdog Timer operation 0: Enables BCC Watchdog Timer operation |
I2C_CONTROL_1 is shown in Table 5-26.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | LOCAL_WRITE_DISABLE | R/W | 0x0 | Disable Remote Writes to Local Registers Setting this bit to a 1 prevents remote writes to local device registers from across the control channel. This prevents writes to the Deserializer registers from an I2C controller attached to the Serializer. Setting this bit does not affect remote access to I2C targets at the Deserializer. |
6:4 | I2C_SDA_HOLD | R/W | 0x1 | Internal SDA Hold Time This field configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 50 nanoseconds. |
3:0 | I2C_FILTER_DEPTH | R/W | 0xC | I2C Glitch Filter Depth This field configures the maximum width of glitch pulses on the SCL and SDA inputs that are rejected. Units are 5 nanoseconds. |
I2C_CONTROL_2 is shown in Table 5-27.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:4 | SDA_OUTPUT_SETUP | R/W | 0x1 | Remote Ack SDA Output Setup When a Control Channel (remote) access is active, this field configures setup time from the SDA output relative to the rising edge of SCL during ACK cycles. Setting this value increases setup time in units of 640ns. The nominal output setup time value for SDA to SCL when this field is 0 is 80ns. |
3:2 | SDA_OUTPUT_DELAY | R/W | 0x0 | SDA Output Delay This field configures additional delay on the SDA output relative to the falling edge of SCL. Setting this value increases output delay in units of 40ns. Nominal output delay values for SCL to SDA are: 00: 240ns 01: 280ns 10: 320ns 11: 360ns |
1 | I2C_BUS_TIMER_SPEEDUP | R/W | 0x0 | Speed up I2C Bus Watchdog Timer 1: Watchdog Timer expires after approximately 50 microseconds 0: Watchdog Timer expires after approximately 1 second. |
0 | I2C_BUS_TIMER_DISABLE | R/W | 0x0 | Disable I2C Bus Watchdog Timer The I2C Watchdog Timer can be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signalling occurs for approximately 1 second, the I2C bus id assumed to be free. If SDA is low and no signaling occurs, the device attempts to clear the bus by driving 9 clocks on SCL |
SCL_HIGH_TIME is shown in Table 5-28.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | SCL_HIGH_TIME | R/W | 0x79 | I2C Controller SCL High Time This field configures the high pulse width of the SCL output when the Serializer is the Controller on the local I2C bus. Units are 40ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL high time with the reference clock at 25MHz + 100ppm. The delay includes 5 additional oscillator clock periods. Min_delay= 39.996ns * (SCL_HIGH_TIME + 5) |
SCL_LOW_TIME is shown in Table 5-29.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | SCL_LOW_TIME | R/W | 0x79 | I2C SCL Low Time This field configures the low pulse width of the SCL output when the Serializer is the Controller on the local I2C bus. This value is also used as the SDA setup time by the I2C Target for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 40ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL low time with the reference clock at 25MHz + 100ppm. The delay includes 5 additional clock periods. Min_delay= 39.996ns * (SCL_LOW_TIME+ 5) |
RX_PORT_CTL is shown in Table 5-30.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | BCC3_MAP | R/W | 0x0 | Map Control Channel 3 to I2C Target
Port 0: I2C Target Port 0 1: I2C Target Port 1 |
6 | BCC2_MAP | R/W | 0x0 | Map Control Channel 2 to I2C Target
Port 0: I2C Target Port 0 1: I2C Target Port 1 |
5 | BCC1_MAP | R/W | 0x0 | Map Control Channel 1 to I2C Target
Port 0: I2C Target Port 0 1: I2C Target Port 1 |
4 | BCC0_MAP | R/W | 0x0 | Map Control Channel 0 to I2C Target
Port 0: I2C Target Port 0 1: I2C Target Port 1 |
3 | PORT3_EN | R/W | 0x1 | Port 3 Receiver Enable 0: Disable Port 3 Receiver 1: Enable Port 3 Receiver |
2 | PORT2_EN | R/W | 0x1 | Port 2 Receiver Enable 0: Disable Port 2 Receiver 1: Enable Port 2 Receiver |
1 | PORT1_EN | R/W | 0x1 | Port 1 Receiver Enable 0: Disable Port 1 Receiver 1: Enable Port 1 Receiver |
0 | PORT0_EN | R/W | 0x1 | Port 0 Receiver Enable 0: Disable Port 0 Receiver 1: Enable Port 0 Receiver |
IO_CTL is shown in Table 5-31.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | SEL3P3V | R/W | 0x0 | 3.3V I/O Select on pins PDB,INTB,I2C 0: 1.8V I/O Supply 1: 3.3V I/O Supply If IO_SUPPLY_MODE_OV is 0, a read of this register returns the detected I/O voltage level. |
6 | IO_SUPPLY_MODE_OV | R/W | 0x0 | Override I/O Supply Mode bit If set to 0, the detected voltage level is used for both SEL3P3V and IO_SUPPLY_MODE controls. If set to 1, the values written to the SEL3P3V and IO_SUPPLY_MODE fields are used. |
5:4 | IO_SUPPLY_MODE | R/W | 0x0 | I/O Supply Mode 00: 1.8V 01: Reserved 10: Reserved 11: 3.3V If IO_SUPPLY_MODE_OV is 0, a read of this register returns the detected I/O voltage level. |
3:0 | RESERVED | R | 0x0 | Reserved |
GPIO_PIN_STS is shown in Table 5-32.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | GPIO_STS | R | 0x0 | GPIO Pin Status This register reads the current values on each of the 8 GPIO pins. Bit 7 reads GPIO7 and bit 0 reads GPIO0. |
GPIO_INPUT_CTL is shown in Table 5-33.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | GPIO7_INPUT_EN | R/W | 0x1 | GPIO7 Input Enable 0: Disabled 1: Enabled |
6 | GPIO6_INPUT_EN | R/W | 0x1 | GPIO6 Input Enable 0: Disabled 1: Enabled |
5 | GPIO5_INPUT_EN | R/W | 0x1 | GPIO5 Input Enable 0: Disabled 1: Enabled |
4 | GPIO4_INPUT_EN | R/W | 0x1 | GPIO4 Input Enable 0: Disabled 1: Enabled |
3 | GPIO3_INPUT_EN | R/W | 0x1 | GPIO3 Input Enable 0: Disabled 1: Enabled |
2 | GPIO2_INPUT_EN | R/W | 0x1 | GPIO2 Input Enable 0: Disabled 1: Enabled |
1 | GPIO1_INPUT_EN | R/W | 0x1 | GPIO1 Input Enable 0: Disabled 1: Enabled |
0 | GPIO0_INPUT_EN | R/W | 0x1 | GPIO0 Input Enable 0: Disabled 1: Enabled |
GPIO0_PIN_CTL is shown in Table 5-34.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | GPIO0_OUT_SEL | R/W | 0x0 | GPIO0 Output Select Determines the output data for the selected source. If GPIO0_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO0_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO0_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO0_OUT_SRC is set to 11x (one of the CSI Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI TX Port Interrupt 111: Reserved |
4:2 | GPIO0_OUT_SRC | R/W | 0x0 | GPIO0 Output Source Select Selects output source for GPIO0 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI TX Port 0 111: CSI TX Port 1 |
1 | GPIO0_OUT_VAL | R/W | 0x0 | GPIO0 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value. |
0 | GPIO0_OUT_EN | R/W | 0x0 | GPIO0 Output Enable 0: Disabled 1: Enabled |
GPIO1_PIN_CTL is shown in Table 5-35.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | GPIO1_OUT_SEL | R/W | 0x0 | GPIO1 Output Select Determines the output data for the selected source. If GPIO1_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO1_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO0_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO1_OUT_SRC is set to 11x (one of the CSI Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI TX Port Interrupt 111: Reserved |
4:2 | GPIO1_OUT_SRC | R/W | 0x0 | GPIO1 Output Source Select Selects output source for GPIO0 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI TX Port 0 111: CSI TX Port 1 |
1 | GPIO1_OUT_VAL | R/W | 0x0 | GPIO1 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value. |
0 | GPIO1_OUT_EN | R/W | 0x0 | GPIO1 Output Enable 0: Disabled 1: Enabled |
GPIO2_PIN_CTL is shown in Table 5-36.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | GPIO2_OUT_SEL | R/W | 0x0 | GPIO2 Output Select Determines the output data for the selected source. If GPIO2_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO2_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO0_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO2_OUT_SRC is set to 11x (one of the CSI Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI TX Port Interrupt 111: Reserved |
4:2 | GPIO2_OUT_SRC | R/W | 0x0 | GPIO2 Output Source Select Selects output source for GPIO0 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI TX Port 0 111: CSI TX Port 1 |
1 | GPIO2_OUT_VAL | R/W | 0x0 | GPIO2 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value. |
0 | GPIO2_OUT_EN | R/W | 0x0 | GPIO2 Output Enable 0: Disabled 1: Enabled |
GPIO3_PIN_CTL is shown in Table 5-37.
Return to the Summary Table.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | GPIO3_OUT_SEL | R/W | 0x0 | GPIO3 Output Select Determines the output data for the selected source. If GPIO3_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO3_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO0_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: Frame Valid signal 101: Line Valid signal 110 - 111: Reserved If GPIO3_OUT_SRC is set to 11x (one of the CSI Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI TX Port Interrupt 111: Reserved |
4:2 | GPIO3_OUT_SRC | R/W | 0x0 | GPIO3 Output Source Select Selects output source for GPIO0 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI TX Port 0 111: CSI TX Port 1 |
1 | GPIO3_OUT_VAL | R/W | 0x0 | GPIO3 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value. |
0 | GPIO3_OUT_EN | R/W | 0x0 | GPIO3 Output Enable 0: Disabled 1: Enabled |
GPIO4_PIN_CTL is shown in Table 5-38.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | GPIO4_OUT_SEL | R/W | 0x0 | GPIO4 Output Select Determines the output data for the selected source. If GPIO4_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO4_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO0_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO4_OUT_SRC is set to 11x (one of the CSI Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI TX Port Interrupt 111: Reserved |
4:2 | GPIO4_OUT_SRC | R/W | 0x0 | GPIO4 Output Source Select Selects output source for GPIO0 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI TX Port 0 111: CSI TX Port 1 |
1 | GPIO4_OUT_VAL | R/W | 0x0 | GPIO4 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value. |
0 | GPIO4_OUT_EN | R/W | 0x0 | GPIO4 Output Enable 0: Disabled 1: Enabled |
GPIO5_PIN_CTL is shown in Table 5-39.
Return to the Summary Table.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | GPIO5_OUT_SEL | R/W | 0x0 | GPIO5 Output Select Determines the output data for the selected source. If GPIO5_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO5_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO0_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO5_OUT_SRC is set to 11x (one of the CSI Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI TX Port Interrupt 111: Reserved |
4:2 | GPIO5_OUT_SRC | R/W | 0x0 | GPIO5 Output Source Select Selects output source for GPIO0 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI TX Port 0 111: CSI TX Port 1 |
1 | GPIO5_OUT_VAL | R/W | 0x0 | GPIO5 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value. |
0 | GPIO5_OUT_EN | R/W | 0x0 | GPIO5 Output Enable 0: Disabled 1: Enabled |
GPIO6_PIN_CTL is shown in Table 5-40.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | GPIO6_OUT_SEL | R/W | 0x0 | GPIO6 Output Select Determines the output data for the selected source. If GPIO6_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO6_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO0_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO6_OUT_SRC is set to 11x (one of the CSI Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI TX Port Interrupt 111: Reserved |
4:2 | GPIO6_OUT_SRC | R/W | 0x0 | GPIO6 Output Source Select Selects output source for GPIO0 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI TX Port 0 111: CSI TX Port 1 |
1 | GPIO6_OUT_VAL | R/W | 0x0 | GPIO6 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value. |
0 | GPIO6_OUT_EN | R/W | 0x0 | GPIO6 Output Enable 0: Disabled 1: Enabled |
GPIO7_PIN_CTL is shown in Table 5-41.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | GPIO7_OUT_SEL | R/W | 0x0 | GPIO7 Output Select Determines the output data for the selected source. If GPIO7_OUT_SRC is set to 0xx (one of the RX Ports), the following selections apply: 000: Received GPIO0 001: Received GPIO1 010: Received GPIO2 011: Received GPIO3 100: RX Port Lock indication 101: RX Port Pass indication 110: Frame Valid signal 111: Line Valid signal If GPIO7_OUT_SRC is set to 100 (Device Status), the following selections apply: 000: Value in GPIO0_OUT_VAL 001: Logical OR of Lock indication from enabled RX ports 010: Logical AND of Lock indication from enabled RX ports 011: Logical AND of Pass indication from enabled RX ports 100: FrameSync signal 101 - 111: Reserved If GPIO7_OUT_SRC is set to 11x (one of the CSI Transmit ports), the following selections apply: 000: Pass (AND of selected RX port status) 001: Pass (OR of selected RX port status) 010: Frame Valid (sending video frame) 011: Line Valid (sending video line) 100: Synchronized - multi-port data is synchronized 101: CSI TX Port Interrupt 111: Reserved |
4:2 | GPIO7_OUT_SRC | R/W | 0x0 | GPIO7 Output Source Select Selects output source for GPIO0 data: 000: RX Port 0 001: RX Port 1 010: RX Port 2 011: RX Port 3 100: Device Status 101: Reserved 110: CSI TX Port 0 111: CSI TX Port 1 |
1 | GPIO7_OUT_VAL | R/W | 0x0 | GPIO7 Output Value This register provides the output data value when the GPIO pin is enabled to output the local register controlled value. |
0 | GPIO7_OUT_EN | R/W | 0x0 | GPIO7 Output Enable 0: Disabled 1: Enabled |
FS_CTL is shown in Table 5-42.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:4 | FS_MODE | R/W | 0x0 | FrameSync Mode 0000: Internal Generated FrameSync, use Back-channel frame clock from port 0 0001: Internal Generated FrameSync, use Back-channel frame clock from port 1 0010: Internal Generated FrameSync, use Back-channel frame clock from port 2 0011: Internal Generated FrameSync, use Back-channel frame clock from port 3 01xx: Internal Generated FrameSync, use 25MHz clock 1000: External FrameSync from GPIO0 1001: External FrameSync from GPIO1 1010: External FrameSync from GPIO2 1011: External FrameSync from GPIO3 1100: External FrameSync from GPIO4 1101: External FrameSync from GPIO5 1110: External FrameSync from GPIO6 1111: External FrameSync from GPIO7 |
3 | FS_SINGLE | RH/W1S | 0x0 | Generate Single FrameSync pulse When this bit is set, a single FrameSync pulse is generated. The system must wait for the full duration of the desired pulse before generating another pulse. When using this feature, the FS_GEN_ENABLE bit must remain set to 0. This bit is self-clearing and always returns 0. |
2 | FS_INIT_STATE | R/W | 0x0 | FrameSync Initial State This register controls the initial state of the FrameSync signal. 0: FrameSync initial state is 0 1: FrameSync initial state is 1 |
1 | FS_GEN_MODE | R/W | 0x0 | FrameSync Generation Mode This control selects between Hi/Lo and 50/50 modes. In Hi/Lo mode, the FrameSync generator uses the FS_HIGH_TIME and FS_LOW_TIME register values to separately control the High and Low periods for the generated FrameSync signal. FrameSync times are based on the settings of the FS_MODE field. In 50/50 mode, the FrameSync generator uses the values in the FS_HIGH_TIME_0, FS_LOW_TIME_1 and FS_LOW_TIME_0 registers as a 24-bit value for both the High and Low periods of the generated FrameSync signal. 0: Hi/Lo 1: 50/50 |
0 | FS_GEN_ENABLE | R/W | 0x0 | FrameSync Generation Enable 0: Disabled 1: Enabled |
FS_HIGH_TIME_1 is shown in Table 5-43.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FRAMESYNC_HIGH_TIME_1 | R/W | 0x0 | FrameSync High Time bits 15:8 The value programmed to the FS_HIGH_TIME register must be reduced by 1 from the desired delay. For example, a value of 0 in the FRAMESYNC_HIGH_TIME field results in a 1 cycle high pulse on the FrameSync signal. |
FS_HIGH_TIME_0 is shown in Table 5-44.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FRAMESYNC_HIGH_TIME_0 | R/W | 0x0 | FrameSync High Time bits 7:0 The value programmed to the FS_HIGH_TIME register must be reduced by 1 from the desired delay. For example, a value of 0 in the FRAMESYNC_HIGH_TIME field results in a 1 cycle high pulse on the FrameSync signal. |
FS_LOW_TIME_1 is shown in Table 5-45.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FRAMESYNC_LOW_TIME_1 | R/W | 0x0 | FrameSync Low Time bits 15:8 The value programmed to the FS_HIGH_TIME register must be reduced by 1 from the desired delay. For example, a value of 0 in the FRAMESYNC_HIGH_TIME field results in a 1 cycle high pulse on the FrameSync signal. |
FS_LOW_TIME_0 is shown in Table 5-46.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FRAMESYNC_LOW_TIME_0 | R/W | 0x0 | FrameSync Low Time bits 7:0 The value programmed to the FS_HIGH_TIME register must be reduced by 1 from the desired delay. For example, a value of 0 in the FRAMESYNC_HIGH_TIME field results in a 1 cycle high pulse on the FrameSync signal. |
MAX_FRM_HI is shown in Table 5-47.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | MAX_FRAME_HI | R/W | 0x0 | CSI-2 Maximum Frame Count bits 15:8 In RAW mode operation, the FPD3 Receiver creates CSI2 video frames. For the Frame Start and Frame End packets of each video frame, a 16-bit frame number field is generated. If the Maximum Frame Count value is set to 0, the frame number is disabled and is always 0. If Maximum Frame Count value is non-zero, the frame number increments for each from 1 up to the Maximum Frame Count value before resetting to 1. |
MAX_FRM_LO is shown in Table 5-48.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | MAX_FRAME_LO | R/W | 0x4 | CSI-2 Maximum Frame Count bits 7:0 In RAW mode operation, the FPD3 Receiver creates CSI2 video frames. For the Frame Start and Frame End packets of each video frame, a 16-bit frame number field is generated. If the Maximum Frame Count value is set to 0, the frame number is disabled and is always 0. If Maximum Frame Count value is non-zero, the frame number increments for each from 1 up to the Maximum Frame Count value before resetting to 1. |
CSI_PLL_CTL is shown in Table 5-49.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:3 | RESERVED | R | 0x0 | Reserved |
2 | RESERVED | R | 0x0 | Reserved |
1:0 | CSI_TX_SPEED | R/W | 0x2 | CSI Transmitter Speed select: Controls the CSI Transmitter frequency. 00: 1.6Gbps serial rate 01: Reserved 10: 800Mbps serial rate 11: 400Mbps serial rate |
FWD_CTL1 is shown in Table 5-50.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | FWD_PORT3_DIS | R/W | 0x1 | Disable forwarding of RX Port 3 0: Forwarding enabled 1: Forwarding disabled |
6 | FWD_PORT2_DIS | R/W | 0x1 | Disable forwarding of RX Port 2 0: Forwarding enabled 1: Forwarding disabled |
5 | FWD_PORT1_DIS | R/W | 0x1 | Disable forwarding of RX Port 1 0: Forwarding enabled 1: Forwarding disabled |
4 | FWD_PORT0_DIS | R/W | 0x1 | Disable forwarding of RX Port 0 0: Forwarding enabled 1: Forwarding disabled |
3 | RX3_MAP | R/W | 0x0 | Map RX Port 3 to CSI-2 Port 0: CSI-2 Port 0 1: CSI-2 Port 1 It is recommended to disable forwarding for a port before changing the port mapping. |
2 | RX2_MAP | R/W | 0x0 | Map RX Port 2 to CSI-2 Port 0: CSI-2 Port 0 1: CSI-2 Port 1 It is recommended to disable forwarding for a port before changing the port mapping. |
1 | RX1_MAP | R/W | 0x0 | Map RX Port 1 to CSI-2 Port 0: CSI-2 Port 0 1: CSI-2 Port 1 It is recommended to disable forwarding for a port before changing the port mapping. |
0 | RX0_MAP | R/W | 0x0 | Map RX Port 0 to CSI-2 Port 0: CSI-2 Port 0 1: CSI-2 Port 1 It is recommended to disable forwarding for a port before changing the port mapping. |
FWD_CTL2 is shown in Table 5-51.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | CSI_REPLICATE | R/W | 0x0 | CSI Replicate Mode When set to a 1, the CSI output from port 0 is also generated on CSI port 1. The same output data is presented on both ports. |
6 | FWD_SYNC_AS_AVAIL | R/W | 0x0 | Synchronized Forwarding As Available During Synchronized Forwarding, each forwarding engine waits for video data to be available from each enabled port, prior to sending the video line. Setting this bit to a 1 allows sending the next video line as the data becomes available. For example, if RX Ports 0 and 1 are being forwarded, port 0 video line is forwarded when the data becomes available, rather than waiting until both ports 0 and ports 1 have video data available. This operation can reduce the likelihood of buffer overflow errors in some conditions. This bit has no affect in video line concatenation mode and only affects video lines (long packets) rather than synchronization packets. This bit applies to both CSI output ports |
5:4 | CSI1_SYNC_FWD | R/W | 0x0 | Enable synchronized forwarding for CSI output port 1 00: Synchronized forwarding disabled 01: Basic Synchronized forwarding enabled 10: Synchronous forwarding with line interleaving 11: Synchronous forwarding with line concatenation Only one of CSI1_RR_FWD and CSI1_SYNC_FWD must be enabled at a time. |
3:2 | CSI0_SYNC_FWD | R/W | 0x0 | Enable synchronized forwarding for CSI output port 0 00: Synchronized forwarding disabled 01: Basic Synchronized forwarding enabled 10: Synchronous forwarding with line interleaving 11: Synchronous forwarding with line concatenation Only one of CSI0_RR_FWD and CSI0_SYNC_FWD must be enabled at a time. |
1 | CSI1_RR_FWD | R/W | 0x1 | Enable best-effort forwarding for CSI output port 1. When this mode is enabled, no attempt is made to synchronize the video traffic. When multiple sources have data available to forward, the data tends to be forwarded in a round-robin fashion. 0: Round robin forwarding disabled 1: Round robin forwarding enabled Only one of CSI1_RR_FWD and CSI1_SYNC_FWD must be enabled at a time. |
0 | CSI0_RR_FWD | R/W | 0x1 | Enable best-effort forwarding for CSI output port 0. When this mode is enabled, no attempt is made to synchronize the video traffic. When multiple sources have data available to forward, the data tends to be forwarded in a round-robin fashion. 0: Round robin forwarding disabled 1: Round robin forwarding enabled Only one of CSI0_RR_FWD and CSI0_SYNC_FWD must be enabled at a time. |
FWD_STS is shown in Table 5-52.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:4 | RESERVED | R | 0x0 | Reserved |
3 | FWD_SYNC_FAIL1 | RC | 0x0 | Forwarding synchronization failed for CSI output port 1 During Synchronized forwarding, this flag indicates a failure of synchronized video has been detected. For this bit to be set, the forwarding process must have previously been successful at sending at least one synchronized video frame. 0: No failure 1: Synchronization failure This bit is cleared on read. |
2 | FWD_SYNC_FAIL0 | RC | 0x0 | Forwarding synchronization failed for CSI output port 0 During Synchronized forwarding, this flag indicates a failure of synchronized video has been detected. For this bit to be set, the forwarding process must have previously been successful at sending at least one synchronized video frame. 0: No failure 1: Synchronization failure This bit is cleared on read. |
1 | FWD_SYNC1 | R | 0x0 | Forwarding synchronized for CSI output port 1 During Synchronized forwarding, this bit indicates that the forwarding engine is currently able to provide synchronized video from enabled Receive ports. This bit is always 0 if Synchronized forwarding is disabled. 0: Video is not synchronized 1: Video is synchronized |
0 | FWD_SYNC0 | R | 0x0 | Forwarding synchronized for CSI output port 0 During Synchronized forwarding, this bit indicates that the forwarding engine is currently able to provide synchronized video from enabled Receive ports. This bit is always 0 if Synchronized forwarding is disabled. 0: Video is not synchronized 1: Video is synchronized |
INTERRUPT_CTL is shown in Table 5-53.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | INT_EN | R/W | 0x0 | Global Interrupt Enable: Enables interrupt on the interrupt signal to the controller. |
6 | RESERVED | R | 0x0 | Reserved |
5 | IE_CSI_TX1 | R/W | 0x0 | CSI Transmit Port 1 Interrupt: Enable interrupt from CSI Transmitter Port 1. |
4 | IE_CSI_TX0 | R/W | 0x0 | CSI Transmit Port 0 Interrupt: Enable interrupt from CSI Transmitter Port 0. |
3 | IE_RX3 | R/W | 0x0 | RX Port 3 Interrupt: Enable interrupt from Receiver Port 3. |
2 | IE_RX2 | R/W | 0x0 | RX Port 2 Interrupt: Enable interrupt from Receiver Port 2. |
1 | IE_RX1 | R/W | 0x0 | RX Port 1 Interrupt: Enable interrupt from Receiver Port 1. |
0 | IE_RX0 | R/W | 0x0 | RX Port 0 Interrupt: Enable interrupt from Receiver Port 0. |
INTERRUPT_STS is shown in Table 5-54.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | INT | R | 0x0 | Global Interrupt: Set if any enabled interrupt is indicated in the individual status bits in this register. The setting of this bit is not dependent on the INT_EN bit in the INTERRUPT_CTL register but does depend on the IE_xxx bits. For example, if IE_RX0 and IS_RX0 are both asserted, the INT bit is set to 1. |
6 | RESERVED | R | 0x0 | Reserved |
5 | IS_CSI_TX1 | R | 0x0 | CSI Transmit Port 1 Interrupt: An interrupt has occurred for CSI Transmitter Port 1. This interrupt is cleared upon reading the CSI_TX_ISR register for CSI Transmit Port 1. |
4 | IS_CSI_TX0 | R | 0x0 | CSI Transmit Port 0 Interrupt: An interrupt has occurred for CSI Transmitter Port 0. This interrupt is cleared upon reading the CSI_TX_ISR register for CSI Transmit Port 0. |
3 | IS_RX3 | R | 0x0 | RX Port 3 Interrupt: An interrupt has occurred for Receive Port 3. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS. |
2 | IS_RX2 | R | 0x0 | RX Port 2 Interrupt: An interrupt has occurred for Receive Port 2. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS. |
1 | IS_RX1 | R | 0x0 | RX Port 1 Interrupt: An interrupt has occurred for Receive Port 1. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS. |
0 | IS_RX0 | R | 0x0 | RX Port 0 Interrupt: An interrupt has occurred for Receive Port 0. This interrupt is cleared by reading the associated status register(s) for the event(s) that caused the interrupt. The status registers are RX_PORT_STS1, RX_PORT_STS2, and CSI_RX_STS. |
TS_CONFIG is shown in Table 5-55.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | FS_POLARITY | R/W | 0x0 | Framesync Polarity Indicates active edge of FrameSync signal 0: Rising edge 1: Falling edge |
5:4 | TS_RES_CTL | R/W | 0x0 | Timestamp Resolution Control 00: 40ns 01: 80ns 10: 160ns 11: 1.0us |
3 | TS_AS_AVAIL | R/W | 0x0 | Timestamp Ready Control 0: Normal operation 1: Indicate timestamps ready as soon as all port timestamps are available |
2 | RESERVED | R | 0x0 | Reserved |
1 | TS_FREERUN | R/W | 0x0 | FreeRun Mode 0: FrameSync mode 1: FreeRun mode |
0 | TS_MODE | R/W | 0x0 | Timestamp Mode 0: Line start 1: Frame start |
TS_CONTROL is shown in Table 5-56.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0x0 | Reserved |
4 | TS_FREEZE | R/W | 0x0 | Freeze Timestamps 0: Normal operation 1: Freeze timestamps Setting this bit freezes timestamps and clears the TS_READY flag. The TS_FREEZE bit must be cleared after reading timestamps to resume operation. |
3 | TS_ENABLE3 | R/W | 0x0 | Timestamp Enable RX Port 3 0: Disabled 1: Enabled |
2 | TS_ENABLE2 | R/W | 0x0 | Timestamp Enable RX Port 2 0: Disabled 1: Enabled |
1 | TS_ENABLE1 | R/W | 0x0 | Timestamp Enable RX Port 1 0: Disabled 1: Enabled |
0 | TS_ENABLE0 | R/W | 0x0 | Timestamp Enable RX Port 0 0: Disabled 1: Enabled |
TS_LINE_HI is shown in Table 5-57.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | TS_LINE_HI | R/W | 0x0 | Timestamp Line, upper 8 bits This field is the line number at which to capture the timestamp when Line Start mode is enabled. For proper operation, the line number must be set to a value greater than 1. During Frame Start mode, if TS_FREERUN is set, the TS_LINE value is used to determine when to begin checking for Frame Start |
TS_LINE_LO is shown in Table 5-58.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | TS_LINE_LO | R/W | 0x0 | Timestamp Line, lower 8 bits This field is the line number at which to capture the timestamp when Line Start mode is enabled. For proper operation, the line number must be set to a value greater than 1. During Frame Start mode, if TS_FREERUN is set, the TS_LINE value is used to determine when to begin checking for Frame Start |
TS_STATUS is shown in Table 5-59.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0x0 | Reserved |
4 | TS_READY | R | 0x0 | Timestamp Ready This flag indicates when timestamps are ready to be read. This flag is cleared when the TS_FREEZE bit is set. |
3 | TS_VALID3 | R | 0x0 | Timestamp Valid, RX Port 3 |
2 | TS_VALID2 | R | 0x0 | Timestamp Valid, RX Port 2 |
1 | TS_VALID1 | R | 0x0 | Timestamp Valid, RX Port 1 |
0 | TS_VALID0 | R | 0x0 | Timestamp Valid, RX Port 0 |
TIMESTAMP_P0_HI is shown in Table 5-60.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | TIMESTAMP_P0_HI | R | 0x0 | Timestamp, upper 8 bits, RX Port 0 |
TIMESTAMP_P0_LO is shown in Table 5-61.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | TIMESTAMP_P0_LO | R | 0x0 | Timestamp, lower 8 bits, RX Port 0 |
TIMESTAMP_P1_HI is shown in Table 5-62.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | TIMESTAMP_P1_HI | R | 0x0 | Timestamp, upper 8 bits, RX Port 1 |
TIMESTAMP_P1_LO is shown in Table 5-63.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | TIMESTAMP_P1_LO | R | 0x0 | Timestamp, lower 8 bits, RX Port 1 |
TIMESTAMP_P2_HI is shown in Table 5-64.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | TIMESTAMP_P2_HI | R | 0x0 | Timestamp, upper 8 bits, RX Port 2 |
TIMESTAMP_P2_LO is shown in Table 5-65.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | TIMESTAMP_P2_LO | R | 0x0 | Timestamp, lower 8 bits, RX Port 2 |
TIMESTAMP_P3_HI is shown in Table 5-66.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | TIMESTAMP_P3_HI | R | 0x0 | Timestamp, upper 8 bits, RX Port 3 |
TIMESTAMP_P3_LO is shown in Table 5-67.
Return to the Summary Table.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | TIMESTAMP_P3_LO | R | 0x0 | Timestamp, lower 8 bits, RX Port 3 |
CSI_PORT_SEL is shown in Table 5-68.
Return to the Summary Table.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0x0 | Reserved |
4 | TX_READ_PORT | R/W | 0x0 | Select TX port for register read This field selects one of the two TX port register blocks for readback. This applies to the subsequent registers prefixed CSI. 0: Port 0 registers 1: Port 1 registers |
3:2 | RESERVED | R | 0x0 | Reserved |
1 | TX_WRITE_PORT_1 | R/W | 0x0 | Write Enable for TX port 1 registers This bit enables writes to TX port 1 registers. Any combination of TX port registers can be written simultaneously. This applies to the subsequent registers prefixed CSI. 0: Writes disabled 1: Writes enabled |
0 | TX_WRITE_PORT_0 | R/W | 0x0 | Write Enable for TX port 0 registers This bit enables writes to TX port 0 registers. Any combination of TX port registers can be written simultaneously. This applies to the subsequent registers prefixed CSI. 0: Writes disabled 1: Writes enabled |
CSI_CTL is shown in Table 5-69.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | CSI_CAL_EN | R/W | 0x0 | Enable initial CSI Skew-Calibration sequence When the initial skew-calibration sequence is enabled, the CSI Transmitter sends the sequence at initialization, prior to sending any HS data. This bit is recommended to be set when operating at 1.6Gbps CSI speed (as configured in the CSI_PLL register). 0: Disabled 1: Enabled |
5:4 | CSI_LANE_COUNT | R/W | 0x0 | CSI lane count 00: 4 lanes 01: 3 lanes 10: 2 lanes 11: 1 lane |
3:2 | CSI_ULP | R/W | 0x0 | Force LP00 state on data/clock lanes 00: Normal operation 01: LP00 state forced only on data lanes 10: Reserved 11: LP00 state forced on data and clock lanes |
1 | CSI_CONTS_CLOCK | R/W | 0x0 | Enable CSI continuous clock mode When enabled, the CSI Transmitter enters continuous clock mode upon transmission of the first packet. 0: Disabled 1: Enabled |
0 | CSI_ENABLE | R/W | 0x0 | Enable CSI output 0: Disabled 1: Enabled Forwarding is recommended to be disabled (via the FWD_CTL1 register) prior to enabling or disabling the CSI output. |
CSI_CTL2 is shown in Table 5-70.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:4 | RESERVED | R | 0x0 | Reserved |
3 | CSI_PASS_MODE | R/W | 0x0 | CSI PASS indication mode Determines whether the CSI Pass indication is for a single port or all enabled ports. 0: Assert PASS if at least one enabled Receive port is providing valid video data 1: Assert PASS only if ALL enabled Receive ports are providing valid video data |
2 | CSI_CAL_INV | R/W | 0x0 | CSI Calibration Inverted Data pattern During the CSI skew-calibration pattern, the CSI Transmitter sends a sequence of 01010101 data (first bit 0). Setting this bit to a 1 inverts the sequence to 10101010 data. |
1 | CSI_CAL_SINGLE | RH/W1S | 0x0 | Enable single periodic CSI Skew-Calibration sequence Setting this bit sends a single skew-calibration sequence from the CSI Transmitter. The skew-calibration sequence has 210 bits in the 1010 bit sequence required for periodic calibration. The calibration sequence is sent at the next idle period on the CSI interface. This bit is self-clearing and resets to 0 after the calibration sequence is sent. |
0 | CSI_CAL_PERIODIC | R/W | 0x0 | Enable periodic CSI Skew-Calibration sequence When the periodic skew-calibration sequence is enabled, the CSI Transmitter sends the periodic skew-calibration sequence following the sending of Frame End packets. 0: Disabled 1: Enabled |
CSI_STS is shown in Table 5-71.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0x0 | Reserved |
4 | TX_PORT_NUM | R | 0x0 | TX Port Number This read-only field indicates the number of the currently selected TX read port. |
3:2 | RESERVED | R | 0x0 | Reserved |
1 | TX_PORT_SYNC | R | 0x0 | TX Port Synchronized Thist bit indicates the CSI Transmit Port is able to properly synchronize input data streams from multiple sources. This bit is 0 if synchronization is disabled via the FWD_CTL2 register. 0: Input streams are not synchronized 1: Input streams are synchronized |
0 | PASS | R | 0x0 | TX Port Pass Indicates valid data is available on at least one port, or on all ports if configured for all port status via the CSI_PASS_MODE bit in the CSI_CTL2 register. The function differs based on mode of operation. In asynchronous operation, the TX_PORT_PASS indicates the CSI port is actively delivering valid video data. The status is cleared based on detection of an error condition that interrupts transmission. During Synchronized forwarding, the TX_PORT_PASS indicates valid data is available for delivery on the CSI TX output. Data can not be delivered if ports are not synchronized. The TX_PORT_SYNC status is a better indicator that valid data is being delivered to the CSI transmit port. |
CSI_TX_ICR is shown in Table 5-72.
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CSI Transmit Interrupt Control Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0x0 | Reserved |
4 | IE_RX_PORT_INT | R/W | 0x0 | RX Port Interrupt Enable Enable interrupt based on receiver port interrupt for the RX Ports being forwarded to the CSI Transmit Port. |
3 | IE_CSI_SYNC_ERROR | R/W | 0x0 | CSI Sync Error interrupt Enable Enable interrupt on CSI Synchronization enable. |
2 | IE_CSI_SYNC | R/W | 0x0 | CSI Synchronized interrupt Enable Enable interrupts on CSI Transmit Port assertion of CSI Synchronized Status. |
1 | IE_CSI_PASS_ERROR | R/W | 0x0 | CSI RX Pass Error interrupt Enable Enable interrupt on CSI Pass Error |
0 | IE_CSI_PASS | R/W | 0x0 | CSI Pass interrupt Enable Enable interrupt on CSI Transmit Port assertion of CSI Pass. |
CSI_TX_ISR is shown in Table 5-73.
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CSI Transmit Interrupt Status Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | RESERVED | R | 0x0 | Reserved |
4 | IS_RX_PORT_INT | R | 0x0 | RX Port Interrupt A Receiver port interrupt has been generated for one of the RX Ports being forwarded to the CSI Transmit Port. A read of the associated port receive status registers clears this interrupt. See the PORT_ISR_HI and PORT_ISR_LO registers for details. |
3 | IS_CSI_SYNC_ERROR | RC | 0x0 | CSI Sync Error interrupt A synchronization error has been detected for multiple video stream inputs to the CSI Transmitter. |
2 | IS_CSI_SYNC | RC | 0x0 | CSI Synchronized interrupt CSI Transmit Port assertion of CSI Synchronized Status. Current status for CSI Sync can be read from the TX_PORT_SYNC flag in the CSI_STS register. |
1 | IS_CSI_PASS_ERROR | RC | 0x0 | CSI RX Pass Error interrupt A deassertion of CSI Pass has been detected on one of the RX Ports being forwarded to the CSI Transmit Port |
0 | IS_CSI_PASS | RC | 0x0 | CSI Pass interrupt CSI Transmit Port assertion of CSI Pass detected. Current status for the CSI Pass indication can be read from the TX_PORT_PASS flag in the CSI_STS register |
SFILTER_CFG is shown in Table 5-74.
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SFILTER Configuration
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:4 | SFILTER_MAX | R/W | 0xA | SFILTER Maximum setting This field controls the maximum SFILTER setting. Allowed values are 0-12 with 6 being the mid point. These values are used during AEQ adaption, but not with dynamic SFILTER control. |
3:0 | SFILTER_MIN | R/W | 0x3 | SFILTER Maximum setting This field controls the maximum SFILTER setting. Allowed values are 0-12, where 6 is the mid point. These values are used during AEQ adaption, but not with dynamic SFILTER control. |
AEQ_CTL is shown in Table 5-75.
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AEQ Control
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6:4 | AEQ_ERR_CTL | R/W | 0x0 | AEQ Error Control Setting any of these bits enables FPD3 error checking during the Adaptive Equalization process. Errors are accumulated over 1/2 of the period of the timer set by the ADAPTIVE_EQ_RELOCK_TIME filed in the AEQ_TEST register. If the number of errors is greater than the programmed threshold (AEQ_ERR_THOLD), the AEQ attempts to increase the EQ setting. The errors can also be checked as part of EQ setting validation if AEQ_2STEP_EN is set. The following errors are checked based on this three bit field: [2] FPD3 clk1/clk0 errors [1] Encoding sequence errors [0] Parity errors |
3 | RESERVED | R | 0x0 | Reserved |
2 | AEQ_2STEP_EN | R/W | 0x0 | AEQ 2-step enable This bit enables a two-step operation as part of the Adaptive EQ algorithm. If disabled, the state machine waits for a programmed period of time, then check status to determine if setting is valid. If enabled, the state machine waits for 1/2 the programmed period, then check for errors over an additional 1/2 the programmed period. If errors occur during the 2nd step, the state machine immediately moves to the next setting. 0: Wait for full programmed delay, then check instantaneous lock value 1: Wait for 1/2 programmed time, then check for errors over 1/2 programmed time. The programmed time is controlled by the ADAPTIVE_EQ_RELOCK_TIME field in the AEQ_TEST register |
1 | AEQ_OUTER_LOOP | R/W | 0x0 | AEQ outer loop control This bit controls whether the Equalizer or SFILTER adaption is the outer loop when the AEQ adaption includes SFILTER adaption. 0: AEQ is inner loop, SFILTER is outer loop 1: AEQ is outer loop, SFILTER is inner loop |
0 | AEQ_SFILTER_EN | R/W | 0x1 | Enable SFILTER Adaption with AEQ Setting this bit allows SFILTER adaption as part of the Adaptive Equalizer algorithm. |
AEQ_ERR_THOLD is shown in Table 5-76.
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AEQ Error Threshold
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | AEQ_ERR_THRESHOLD | R/W | 0x1 | AEQ Error Threshold This register controls the error threshold to determine when to re-adapt the EQ settings. This register must not be programmed to a value of 0. |
FPD3_PORT_SEL is shown in Table 5-77.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | PHYS_PORT_NUM | R | 0x0 | Physical port number This field porvides the physical port connection when reading from a remote device via the Bidirectional Control Channel. When accessed via local I2C interfaces, the value returned is always 0. When accessed via Bidirectional Control Channel, the value returned is the port number of the Receive port connection. |
5:4 | RX_READ_PORT | R/W | 0x0 | Select RX port for register read This field selects one of the four RX port register blocks for readback. This applies to all paged FPD3 Receiver port registers. 00: Port 0 registers 01: Port 1 registers 10: Port 2 registers 11: Port 3 registers When accessed via local I2C interfaces, the default setting is 0. When accessed via Bidirectional Control Channel, the default value is the port number of the Receive port connection. |
3 | RX_WRITE_PORT_3 | R/W | 0x0 | Write Enable for RX port 3 registers This bit enables writes to RX port 3 registers. Any combination of RX port registers can be written simultaneously. This applies to all paged FPD3 Receiver port registers. 0: Writes disabled 1: Writes enabled When accessed via Bidirectional Control Channel, the default value is 1 if accessed over RX port 3. |
2 | RX_WRITE_PORT_2 | R/W | 0x0 | Write Enable for RX port 2 registers This bit enables writes to RX port 2 registers. Any combination of RX port registers can be written simultaneously. This applies to all paged FPD3 Receiver port registers. 0: Writes disabled 1: Writes enabled When accessed via Bidirectional Control Channel, the default value is 1 if accessed over RX port 2. |
1 | RX_WRITE_PORT_1 | R/W | 0x0 | Write Enable for RX port 1 registers This bit enables writes to RX port 1 registers. Any combination of RX port registers can be written simultaneously. This applies to all paged FPD3 Receiver port registers. 0: Writes disabled 1: Writes enabled When accessed via Bidirectional Control Channel, the default value is 1 if accessed over RX port 1. |
0 | RX_WRITE_PORT_0 | R/W | 0x0 | Write Enable for RX port 0 registers This bit enables writes to RX port 0 registers. Any combination of RX port registers can be written simultaneously. This applies to all paged FPD3 Receiver port registers. 0: Writes disabled 1: Writes enabled When accessed via Bidirectional Control Channel, the default value is 1 if accessed over RX port 0. |
RX_PORT_STS1 is shown in Table 5-78.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | RX_PORT_NUM | R | 0x0 | RX Port Number This read-only field indicates the number of the currently selected RX read port. |
5 | BCC_CRC_ERROR | RC | 0x0 | Bidirectional Control Channel CRC Error Detected This bit indicates a CRC error has been detected in the forward control channel. If this bit is set, an error can have occurred in the control channel operation. This bit is cleared on read. |
4 | LOCK_STS_CHG | RC | 0x0 | Lock Status Changed This bit is set if a change in receiver lock status has been detected since the last read of this register. Current lock status is available in the LOCK_STS bit of this register This bit is cleared on read. |
3 | BCC_SEQ_ERROR | RC | 0x0 | Bidirectional Control Channel Sequence Error Detected This bit indicates a sequence error has been detected in the forward control channel. If this bit is set, an error can have occurred in the control channel operation. This bit is cleared on read. |
2 | PARITY_ERROR | R | 0x0 | FPD3 parity errors detected This flag is set when the number of parity errors detected is greater than the threshold programmed in the PAR_ERR_THOLD registers. 1: Number of FPD3 parity errors detected is greater than the threshold 0: Number of FPD3 parity errors is below the threshold This bit is cleared when the RX_PAR_ERR_HI/LO registers are cleared. This bit is cleared on read. |
1 | PORT_PASS | R | 0x0 | Receiver PASS indication This bit indicates the current status of the Receiver PASS indication. The requirements for setting the Receiver PASS indication are controlled by the PORT_PASS_CTL register. 1: Receive input has met PASS criteria 0: Receive input does not meet PASS criteria |
0 | LOCK_STS | R | 0x0 | FPD-Link III receiver is locked to incoming data 1: Receiver is locked to incoming data 0: Receiver is not locked |
RX_PORT_STS2 is shown in Table 5-79.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | LINE_LEN_UNSTABLE | RC | 0x0 | Line Length Unstable If set, this bit indicates the line length was detected as unstable during a previous video frame. The line length is considered to be stable if all the lines in the video frame have the same length. This flag remains set until read. |
6 | LINE_LEN_CHG | RC | 0x0 | Line Length Changed 1: Change of line length detected 0: Change of line length not detected This bit is cleared on read. |
5 | FPD3_ENCODE_ERROR | RC | 0x0 | FPD3 Encoder error detected If set, this flag indicates an error in the FPD-Link III encoding has been detected by the FPD-Link III receiver. This bit is cleared on read. Note, to detect FPD3 Encoder errors, the LINK_ERROR_COUNT must be enabled with a LINK_ERR_THRESH value greater than 1. Otherwise, the loss of Receiver Lock prevents detection of the Encoder error. |
4 | BUFFER_ERROR | RC | 0x0 | Packet buffer error detected. If this bit is set, an overflow condition has occurred on the packet buffer FIFO. 1: Packet Buffer error detected 0: No Packet Buffer errors detected This bit is cleared on read. |
3 | RESERVED | R | 0x0 | Reserved |
2 | FREQ_STABLE | R | 0x0 | FPD3 Frequency measurement stable Indicates the FPD3 input clock frequency is stable. Setting of this flag is dependent on the stability control settings in the FREQ_DET_CTL register. |
1 | NO_FPD3_CLK | R | 0x0 | No FPD-Link III input clock detected When set, this bit indicates that no FPD3 Clock has been detected. This bit is set if the input frequency is below the setting programmed in the FREQ_LO_THR setting in the FREQ_DET_CTL register. |
0 | LINE_CNT_CHG | RC | 0x0 | Line Count Changed 1: Change of line count detected 0: Change of line count not detected This bit is cleared on read. |
RX_FREQ_HIGH is shown in Table 5-80.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FREQ_CNT_HIGH | R | 0x0 | Frequency Counter High Byte (MHz) The Frequency counter reports the measured frequency for the FPD3 Receiver. This portion of the field is the integer value in MHz. |
RX_FREQ_LOW is shown in Table 5-81.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FREQ_CNT_LOW | R | 0x0 | Frequency Counter Low Byte (1/256MHz) The Frequency counter reports the measured frequency for the FPD3 Receiver. This portion of the field is the fractional value in 1/256MHz. |
RX_PAR_ERR_HI is shown in Table 5-82.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PAR_ERROR_BYTE_1 | R | 0x0 | Number of FPD3 parity errors – 8 most significant bits The parity error counter registers return the number of data parity errors that have been detected on the FPD3 Receiver data since the last detection of valid lock or last read of the RX_PAR_ERR_LO register. For accurate reading of the parity error count, disable the RX PARITY CHECKER ENABLE bit in register 0x2 prior to reading the parity error count registers. This register is cleared upon reading the RX_PAR_ERR_LO register. This register is cleared on setting the RX PARITY CHECKER ENABLE bit in register 0x2 |
RX_PAR_ERR_LO is shown in Table 5-83.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | PAR_ERROR_BYTE_0 | RC | 0x0 | Number of FPD3 parity errors – 8 least significant bits The parity error counter registers return the number of data parity errors that have been detected on the FPD3 Receiver data since the last detection of valid lock or last read of the RX_PAR_ERR_LO register. For accurate reading of the parity error count, disable the RX PARITY CHECKER ENABLE bit in register 0x2 prior to reading the parity error count registers. This register is cleared on read. This register is cleared on setting the RX PARITY CHECKER ENABLE bit in register 0x2 |
BIST_ERR_COUNT is shown in Table 5-84.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | BIST_ERROR_COUNT | R | 0x0 | Bist Error Count Returns BIST error count |
BCC_CONFIG is shown in Table 5-85.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | I2C_PASS_THROUGH_ALL | R/W | 0x0 | I2C Pass-Through All Transactions 0: Disabled 1: Enabled |
6 | I2C_PASS_THROUGH | R/W | 0x0 | I2C Pass-Through to Serializer if decode matches 0: Pass-Through Disabled 1: Pass-Through Enabled |
5 | AUTO_ACK_ALL | R/W | 0x0 | Automatically Acknowledge all I2C writes independent of the forward channel lock state or status of the remote Acknowledge 1: Enable 0: Disable |
4 | BC_ALWAYS_ON | R/W | 0x1 | Back channel enable 1: Back channel is always enabled independent of I2C_PASS_THROUGH and I2C_PASS_THROUGH_ALL 0: Back channel enable requires setting of either I2C_PASS_THROUGH and I2C_PASS_THROUGH_ALL This bit can only be written via a local I2C Controller. |
3 | BC_CRC_GENERATOR_ENABLE | R/W | 0x1 | Back Channel CRC Generator Enable 0: Disable 1: Enable |
2:0 | BC_FREQ_SELECT | R/W | 0x0 | Back Channel Frequency Select 000: 2.5Mbps (default for DS90UB913 compatibility) 001: 1.5625Mbps 010 - 111: Reserved Note that changing this setting can result in some errors on the back channel for a short period of time. If set over the control channel, the Deserializer must first be programmed to Auto-Ack operation to avoid a control channel timeout due to lack of response from the Serializer. |
DATAPATH_CTL1 is shown in Table 5-86.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | OVERRIDE_FC_CONFIG | R/W | 0x0 | 1: Disable loading of the DATAPATH_CTL registers from the forward channel, keeping locally written values intact 0: Allow forward channel loading of DATAPATH_CTL registers |
6:2 | RESERVED | R | 0x0 | Reserved |
1:0 | FC_GPIO_EN | R/W | 0x0 | Forward Channel GPIO Enable Configures the number of enabled forward channel GPIOs 00: GPIOs disabled 01: One GPIO 10: Two GPIOs 11: Four GPIOs This field is normally loaded from the remote serializer. This field can be overwritten if the OVERRIDE_FC_CONFIG bit in this register is 1. |
DATAPATH_CTL2 is shown in Table 5-87.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | RESERVED | R | 0x0 | Reserved This field is normally loaded from the remote serializer. This field can be overwritten if the OVERRIDE_FC_CONFIG bit in the DATAPATH_CTL0 register is 1. |
SER_ID is shown in Table 5-88.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | SER_ID | R/W | 0x0 | Remote Serializer ID This field is normally loaded automatically from the remote Serializer. |
0 | FREEZE_DEVICE_ID | R/W | 0x0 | Freeze Serializer Device ID Prevent auto-loading of the Serializer Device ID from the Forward Channel. The ID is frozen at the value written. |
SER_ALIAS_ID is shown in Table 5-89.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | SER_ALIAS_ID | R/W | 0x0 | 7-bit Remote Serializer Alias ID Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Deserializer. The transaction is remapped to the address specified in the Target ID register. A value of 0 in this field disables access to the remote I2C Target. |
0 | SER_AUTO_ACK | R/W | 0x0 | Automatically Acknowledge all I2C writes to the remote Serializer independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable |
TARGET_ID_0 is shown in Table 5-90.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ID0 | R/W | 0x0 | 7-bit Remote Target Device ID 0 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID0, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. |
0 | RESERVED | R | 0x0 | Reserved. |
TARGET_ID_1 is shown in Table 5-91.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ID1 | R/W | 0x0 | 7-bit Remote Target Device ID 1 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID1, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. |
0 | RESERVED | R | 0x0 | Reserved. |
TARGET_ID_2 is shown in Table 5-92.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ID2 | R/W | 0x0 | 7-bit Remote Target Device ID 2 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID2, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. |
0 | RESERVED | R | 0x0 | Reserved. |
TARGET_ID_3 is shown in Table 5-93.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ID3 | R/W | 0x0 | 7-bit Remote Target Device ID 3 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID3, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. |
0 | RESERVED | R | 0x0 | Reserved. |
TARGET_ID_4 is shown in Table 5-94.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ID4 | R/W | 0x0 | 7-bit Remote Target Device ID 4 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID4, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. |
0 | RESERVED | R | 0x0 | Reserved. |
TARGET_ID_5 is shown in Table 5-95.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ID5 | R/W | 0x0 | 7-bit Remote Target Device ID 5 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID5, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. |
0 | RESERVED | R | 0x0 | Reserved. |
TARGET_ID_6 is shown in Table 5-96.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ID6 | R/W | 0x0 | 7-bit Remote Target Device ID 6 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID6, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. |
0 | RESERVED | R | 0x0 | Reserved. |
TARGET_ID_7 is shown in Table 5-97.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ID7 | R/W | 0x0 | 7-bit Remote Target Device ID 7 Configures the physical I2C address of the remote I2C Target device attached to the remote Serializer. If an I2C transaction is addressed to the Target Alias ID7, the transaction is remapped to this address before passing the transaction across the Bidirectional Control Channel to the Serializer. |
0 | RESERVED | R | 0x0 | Reserved. |
TARGET_ALIAS_0 is shown in Table 5-98.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ALIAS_ID0 | R/W | 0x0 | 7-bit Remote Target Device Alias ID 0 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID0 register. A value of 0 in this field disables access to the remote I2C Target. |
0 | TARGET_AUTO_ACK_0 | R/W | 0x0 | Automatically Acknowledge all I2C writes to the remote Target 0 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable |
TARGET_ALIAS_1 is shown in Table 5-99.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ALIAS_ID1 | R/W | 0x0 | 7-bit Remote Target Device Alias ID 1 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID1 register. A value of 0 in this field disables access to the remote I2C Target. |
0 | TARGET_AUTO_ACK_1 | R/W | 0x0 | Automatically Acknowledge all I2C writes to the remote Target 1 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable |
TARGET_ALIAS_2 is shown in Table 5-100.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ALIAS_ID2 | R/W | 0x0 | 7-bit Remote Target Device Alias ID 2 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID2 register. A value of 0 in this field disables access to the remote I2C Target. |
0 | TARGET_AUTO_ACK_2 | R/W | 0x0 | Automatically Acknowledge all I2C writes to the remote Target 2 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable |
TARGET_ALIAS_3 is shown in Table 5-101.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ALIAS_ID3 | R/W | 0x0 | 7-bit Remote Target Device Alias ID 3 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID3 register. A value of 0 in this field disables access to the remote I2C Target. |
0 | TARGET_AUTO_ACK_3 | R/W | 0x0 | Automatically Acknowledge all I2C writes to the remote Target 3 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable |
TARGET_ALIAS_4 is shown in Table 5-102.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ALIAS_ID4 | R/W | 0x0 | 7-bit Remote Target Device Alias ID 4 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID4 register. A value of 0 in this field disables access to the remote I2C Target. |
0 | TARGET_AUTO_ACK_4 | R/W | 0x0 | Automatically Acknowledge all I2C writes to the remote Target 4 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable |
TARGET_ALIAS_5 is shown in Table 5-103.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ALIAS_ID5 | R/W | 0x0 | 7-bit Remote Target Device Alias ID 5 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID5 register. A value of 0 in this field disables access to the remote I2C Target. |
0 | TARGET_AUTO_ACK_5 | R/W | 0x0 | Automatically Acknowledge all I2C writes to the remote Target 5 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable |
TARGET_ALIAS_6 is shown in Table 5-104.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ALIAS_ID6 | R/W | 0x0 | 7-bit Remote Target Device Alias ID 6 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID6 register. A value of 0 in this field disables access to the remote I2C Target. |
0 | TARGET_AUTO_ACK_6 | R/W | 0x0 | Automatically Acknowledge all I2C writes to the remote Target 6 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable |
TARGET_ALIAS_7 is shown in Table 5-105.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | TARGET_ALIAS_ID7 | R/W | 0x0 | 7-bit Remote Target Device Alias ID 7 Configures the decoder for detecting transactions designated for an I2C Target device attached to the remote Serializer. The transaction is remapped to the address specified in the Target ID7 register. A value of 0 in this field disables access to the remote I2C Target. |
0 | TARGET_AUTO_ACK_7 | R/W | 0x0 | Automatically Acknowledge all I2C writes to the remote Target 7 independent of the forward channel lock state or status of the remote Serializer Acknowledge 1: Enable 0: Disable |
PORT_CONFIG is shown in Table 5-106.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | RESERVED | R | 0x0 | Reserved |
5 | RESERVED | R | 0x0 | Reserved |
4 | RESERVED | R | 0x0 | Reserved |
3 | DISCARD_1ST_LINE_ON_ERR | R/W | 0x1 | In RAW Mode, Discard first video line if FV to LV setup time is not met. 0: Forward truncated 1st video line 1: Discard truncated 1st video line |
2 | RESERVED | R | X | Reserved |
1:0 | FPD3_MODE | R/W | 0x0 | FPD3 Input Mode 00: Reserved 01: RAW12 Mode LF (DS90UB913A-Q1 / DS90UB933- Q1 compatible) 10: RAW12 Mode HF (DS90UB913A-Q1 / DS90UB933- Q1 compatible) 11: RAW10 Mode (DS90UB913A-Q1 / DS90UB933- Q1 compatible) |
BC_GPIO_CTL0 is shown in Table 5-107.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:4 | BC_GPIO1_SEL | R/W | 0x8 | Back channel GPIO1 Select: Determines the data sent on GPIO1 for the port back channel. 0xxx: Pin GPIOx where x is BC_GPIO1_SEL[2:0] 1000: Constant value of 0 1001: Constant value of 1 1010: FrameSync signal 1011 - 1111: Reserved |
3:0 | BC_GPIO0_SEL | R/W | 0x8 | Back channel GPIO0 Select: Determines the data sent on GPIO0 for the port back channel. 0xxx: Pin GPIOx where x is BC_GPIO0_SEL[2:0] 1000: Constant value of 0 1001: Constant value of 1 1010: FrameSync signal 1011 - 1111: Reserved |
BC_GPIO_CTL1 is shown in Table 5-108.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:4 | BC_GPIO3_SEL | R/W | 0x8 | Back channel GPIO3 Select: Determines the data sent on GPIO3 for the port back channel. 0xxx: Pin GPIOx where x is BC_GPIO3_SEL[2:0] 1000: Constant value of 0 1001: Constant value of 1 1010: FrameSync signal 1011 - 1111: Reserved |
3:0 | BC_GPIO2_SEL | R/W | 0x8 | Back channel GPIO2 Select: Determines the data sent on GPIO2 for the port back channel. 0xxx: Pin GPIOx where x is BC_GPIO2_SEL[2:0] 1000: Constant value of 0 1001: Constant value of 1 1010: FrameSync signal 1011 - 1111: Reserved |
RAW10_ID is shown in Table 5-109.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | RAW10_VC | R/W | 0x0 | RAW10 Mode Virtual Channel This field configures the CSI Virtual Channel assigned to the port when receiving RAW10 data. The field value defaults to the FPD-Link III receive port number (0, 1, 2, or 3) |
5:0 | RAW10_DT | R/W | 0x2B | RAW10 Data Type This field configures the CSI data type used in RAW10 mode. The default of 0x2B matches the CSI specification. |
RAW12_ID is shown in Table 5-110.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | RAW12_VC | R/W | 0x0 | RAW12 Mode Virtual Channel This field configures the CSI Virtual Channel assigned to the port when receiving RAW12 data. The field value defaults to the FPD-Link III receive port number (0, 1, 2, or 3) |
5:0 | RAW12_DT | R/W | 0x2C | RAW12 Data Type This field configures the CSI data type used in RAW12 mode. The default of 0x2C matches the CSI specification. |
LINE_COUNT_1 is shown in Table 5-111.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | LINE_COUNT_HI | R | 0x0 | High byte of Line Count The Line Count reports the line count for the most recent video frame. When interrupts are enabled for the Line Count (via the IE_LINE_CNT_CHG register bit), the Line Count value is frozen until read. |
LINE_COUNT_0 is shown in Table 5-112.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | LINE_COUNT_LO | R | 0x0 | Low byte of Line Count The Line Count reports the line count for the most recent video frame. When interrupts are enabled for the Line Count (via the IE_LINE_CNT_CHG register bit), the Line Count value is frozen until read. In addition, when reading the LINE_COUNT registers, the LINE_COUNT_LO is latched upon reading LINE_COUNT_HI to ensure consistency between the two portions of the Line Count. |
LINE_LEN_1 is shown in Table 5-113.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | LINE_LEN_HI | R | 0x0 | High byte of Line Length The Line Length reports the line length recorded during the most recent video frame. If line length is not stable during the frame, this register reports the length of the last line in the video frame. When interrupts are enabled for the Line Length (via the IE_LINE_LEN_CHG register bit), the Line Length value is frozen until read. |
LINE_LEN_0 is shown in Table 5-114.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | LINE_LEN_LO | R | 0x0 | Low byte of Line Length The Line Length reports the lenth of the most recent video line. When interrupts are enabled for the Line Length (via the IE_LINE_LEN_CHG register bit), the Line Length value is frozen until read. In addition, when reading the LINE_LEN registers, the LINE_LEN_LO is latched upon reading LINE_LEN_HI to ensure consistency between the two portions of the Line Length. |
FREQ_DET_CTL is shown in Table 5-115.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | FREQ_HYST | R/W | 0x3 | Frequency Detect Hysteresis: The Frequency detect hysteresis controls reporting of the FPD3 Clock frequency stability via the FREQ_STABLE status in the RX_PORT_STS2 register. The frequency is considered stable when the frequency remains within a range of +/- the FREQ_HYST value from the previous measurement. The FREQ_HYST setting is in MHz. |
5:4 | FREQ_STABLE_THR | R/W | 0x0 | Frequency Stability Threshold: The Frequency detect circuit can be used to detect a stable clock frequency. The Stability Threshold determines the amount of time required for the clock frequency to stay within the FREQ_HYST range to be considered stable: 00: 40us 01: 80us 10: 320us 11: 1.28ms |
3:0 | FREQ_LO_THR | R/W | 0x5 | Frequency Low Threshold |
MAILBOX_1 is shown in Table 5-116.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | MAILBOX_0 | R/W | 0x0 | Mailbox Register This register is an unused read/write register that can be used for any purpose such as passing messages between I2C controllers on opposite ends of the link. |
MAILBOX_2 is shown in Table 5-117.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | MAILBOX_1 | R/W | 0x1 | Mailbox Register This register is an unused read/write register that can be used for any purpose such as passing messages between I2C controllers on opposite ends of the link. |
PORT_CONFIG2 is shown in Table 5-118.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | RAW10_8BIT_CTL | R/W | 0x0 | Raw10 8-bit mode When Raw10 Mode is enabled for the port, the input data is processed as 8-bit data and packed accordingly for transmission over CSI. 00: Normal Raw10 Mode 01: Reserved 10: 8-bit processing using upper 8 bits 11: 8-bit processing using lower 8 bits |
5 | DISCARD_ON_PAR_ERR | R/W | 0x1 | Discard frames on Parity Error 0: Forward packets with parity errors 1: Truncate Frames if a parity error is detected |
4 | DISCARD_ON_LINE_SIZE | R/W | 0x0 | Discard frames on Line Size 0: Allow changes in Line Size within packets 1: Truncate Frames if a change in line size is detected |
3 | DISCARD_ON_FRAME_SIZE | R/W | 0x0 | Discard frames on change in Frame Size When enabled, a change in the number of lines in a frame results in truncation of the packet. The device resumes forwarding video frames based on the PASS_THRESHOLD setting in the PORT_PASS_CTL register. 0: Allow changes in Frame Size 1: Truncate Frames if a change in frame size is detected |
2 | RESERVED | R | 0x0 | Reserved |
1 | LV_POLARITY | R/W | 0x0 | LineValid Polarity This register indicates the expected polarity for the LineValid indication received in Raw mode. 1: LineValid is low for the duration of the video line 0: LIneValid is high for the duration of the video line |
0 | FV_POLARITY | R/W | 0x0 | FrameValid Polarity This register indicates the expected polarity for the FrameValid indication received in Raw mode. 1: FrameValid is low for the duration of the video frame 0: FrameValid is high for the duration of the video frame |
PORT_PASS_CTL is shown in Table 5-119.
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Port Pass Control Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | PASS_DISCARD_EN | R/W | 0x0 | Pass Discard Enable Discard packets if PASS is not indicated. 0: Ignore PASS for forwarding packets 1: Discard packets when PASS is not true |
6 | RESERVED | R | 0x0 | Reserved |
5 | PASS_LINE_CNT | R/W | 0x0 | Pass Line Count Control This register controls whether the device includes line count in qualification of the Pass indication: 0: Don't check line count 1: Check line count When checking line count, Pass is deasserted upon detection of a change in the number of video lines per frame. Pass is not reasserted until the PASS_THRESHOLD setting is met. |
4 | PASS_LINE_SIZE | R/W | 0x0 | Pass Line Size Control This register controls whether the device includes line size in qualification of the Pass indication: 0: Don't check line size 1: Check line size When checking line size, Pass is deasserted upon detection of a change in video line size. Pass is not reasserted until the PASS_THRESHOLD setting is met. |
3 | PASS_PARITY_ERR | R/W | 0x0 | Parity Error Mode If this bit is set to 0, the port Pass indication is deasserted for every parity error detected on the FPD3 Receive interface. If this bit is set to a 1, the port Pass indication is cleared on a parity error and remain clear until the PASS_THRESHOLD is met. |
2 | PASS_WDOG_DIS | R/W | 0x0 | RX Port Pass Watchdog disable When enabled, if the FPD Receiver does not detect a valid frame end condition within two video frame periods, the Pass indication is deasserted. The watchdog timer does not have any effect if the PASS_THRESHOLD is set to 0. 0: Enable watchdog timer for RX Pass 1: Disable watchdog timer for RX Pass |
1:0 | PASS_THRESHOLD | R/W | 0x0 | Pass Threshold Register This register controls the number of valid frames before asserting the port Pass indication. If set to 0, PASS is asserted after Receiver Lock detect. If non-zero, PASS is asserted following reception of the programmed number of valid frames. |
IND_ACC_CTL is shown in Table 5-120.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0x0 | Reserved |
5:2 | IA_SEL | R/W | 0x0 | Indirect Access Register Select: Selects target for register access 0000: Pattern Generator and CSI-2 Registers xxxx: RESERVED |
1 | IA_AUTO_INC | R/W | 0x0 | Indirect Access Auto Increment: Enables auto-increment mode. Upon completion of a read or write, the register address automatically increments by 1 |
0 | IA_READ | R/W | 0x0 | Indirect Access Read: Setting this allows generation of a read strobe to the selected register block upon setting of the IND_ACC_ADDR register. In auto-increment mode, read strobes are also asserted following a read of the IND_ACC_DATA register. This function is only required for blocks that need to pre-fetch register data. |
IND_ACC_ADDR is shown in Table 5-121.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | IA_ADDR | R/W | 0x0 | Indirect Access Register Offset: This register contains the 8-bit register offset for the indirect access. |
IND_ACC_DATA is shown in Table 5-122.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | IA_DATA | R/W | 0x0 | Indirect Access Data: Writing this register causes an indirect write of the IND_ACC_DATA value to the selected analog block register. Reading this register returns the value of the selected block register |
BIST_CTL is shown in Table 5-123.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | BIST_OUT_MODE | R/W | 0x0 | BIST Output Mode 00: No toggling 01: Alternating 1/0 toggling 1x: Toggle based on BIST data |
5:4 | RESERVED | R | 0x0 | Reserved |
3 | BIST_PIN_CONFIG | R/W | 0x1 | Bist Configured through Pin. 1: Bist configured through pin. 0: Bist configured through bits 2:0 in this register |
2:1 | BIST_CLOCK_SOURCE | R/W | 0x0 | BIST Clock Source This register field selects the BIST Clock Source at the Serializer. These register bits are automatically written to the CLOCK SOURCE bits (register offset 0x14) in the Serializer after BIST is enabled. See the appropriate Serializer register descriptions for details. Note: When connected to a DS90UB913A, a setting of 0x3 can result in a clock frequency that is too slow for proper recovery. |
0 | BIST_EN | R/W | 0x0 | BIST Control 1: Enabled 0: Disabled |
PAR_ERR_CTRL is shown in Table 5-124.
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CSI TX Clock Polarity
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | RESERVED | R | 0x0 | Reserved |
5 | PAR_ERR_CNTR_MODE | R/W | 0x0 | Parity Error Counter Mode 0: Clear Parity Error counter if receiver is not locked 1: Maintain Parity Error count value through loss of lock |
4 | DIS_LINK_PAR | R/W | 0x1 | Disable checking of Parity Errors when checking for FPD-Link Lock 0: Parity errors prevent assertion of forward channel lock detect (RX Lock). 1: Parity errors do NOT prevent assertion of forward channel lock detect (RX Lock). This is the default mode of the device. |
3 | DIS_LINKLOSS_PAR | R/W | 0x1 | Disable checking of Parity Errors when checking for loss of link 0: Parity errors prevent assertion of forward channel loss of link (RX Lock). 1: Parity errors do NOT prevent assertion of forward channel loss of link (RX Lock). This is the default mode of the device. |
2 | RESERVED | R | 0x0 | Reserved |
1 | RESERVED | R | 0x0 | Reserved |
0 | RESERVED | R | 0x0 | Reserved |
MODE_IDX_STS is shown in Table 5-125.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | IDX_DONE | R | 0x1 | IDX Done: If set, indicates the IDX decode has completed and latched into the IDX status bits. |
6:4 | IDX | R | 0x0 | IDX Decode 3-bit decode from IDX pin |
3 | MODE_DONE | R | 0x1 | MODE Done: If set, indicates the MODE decode has completed and latched into the MODE status bits. |
2:0 | MODE | R | 0x0 | MODE Decode 3-bit decode from MODE pin |
LINK_ERROR_COUNT is shown in Table 5-126.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0x0 | Reserved |
5 | LINK_SFIL_WAIT | R/W | 0x0 | During SFILTER adaption, setting this bit causes the Lock detect circuit to ignore errors during the SFILTER wait period after the SFILTER control is updated. 1: Errors during SFILTER Wait period are ignored 0: Errors during SFILTER Wait period are not ignored and can cause loss of Lock |
4 | LINK_ERR_COUNT_EN | R/W | 0x0 | Enable serial link data integrity error count 1: Enable error count 0: DISABLE |
3:0 | LINK_ERR_THRESH | R/W | 0x3 | Link error count threshold. The Link Error Counter monitors the forward channel link and determines when link is dropped. If the error counter is enabled, the deserializer loses lock once the error counter reaches the LINK_ERR_THRESH value. If the link error counter is disabled, the deserializer loses lock after one error. The control bits in PAR_ERR_CTRL register can be used to disable error conditions individually. |
FV_MIN_TIME is shown in Table 5-127.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FRAME_VALID_MIN | R/W | 0x80 | Frame Valid Minimum Time This register controls the minimum time the FrameValid (FV) must be active before the Raw mode FPD3 receiver generates a FrameStart packet. Duration is in FPD3 clock periods. |
GPIO_PD_CTL is shown in Table 5-128.
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GPIO Pulldown control register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | GPIO7_PD_DIS | R/W | 0x0 | GPI7 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor is also disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor |
6 | GPIO6_PD_DIS | R/W | 0x0 | GPIO6 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor is also disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor |
5 | GPIO5_PD_DIS | R/W | 0x0 | GPIO5 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor is also disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor |
4 | GPIO4_PD_DIS | R/W | 0x0 | GPIO4 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor is also disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor |
3 | GPIO3_PD_DIS | R/W | 0x0 | GPIO3 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor is also disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor |
2 | GPIO2_PD_DIS | R/W | 0x0 | GPIO2 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor is also disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor |
1 | GPIO1_PD_DIS | R/W | 0x0 | GPIO1 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor is also disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor |
0 | GPIO0_PD_DIS | R/W | 0x0 | GPIO0 Pull-down Resistor Disable: The GPIO pins by default include a pulldown resistor that is automatically enabled when the GPIO is not in an output mode. When this bit is set, the pulldown resistor is also disabled when the GPIO pin is in an input only mode. 1: Disable GPIO pull-down resistor 0: Enable GPIO pull-down resistor |
PORT_DEBUG is shown in Table 5-129.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | RESERVED | R | 0x0 | Reserved |
5 | SER_BIST_ACT | R | 0x0 | Serializer BIST active This register indicates the Serializer is in BIST mode. If the Deserializer is not in BIST mode, this could indicate an error condition. |
4 | RESERVED | R | 0x0 | Reserved |
3 | RESERVED | R | 0x0 | Reserved |
2 | RESERVED | R | 0x0 | Reserved |
1 | RESERVED | R | 0x0 | Reserved |
0 | RESERVED | R | 0x0 | Reserved |
AEQ_CTL2 is shown in Table 5-130.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | ADAPTIVE_EQ_RELOCK_TIME | R/W | 0x4 | Time to wait for lock before incrementing the EQ to next setting 000: 164us 001: 328us 010: 655us 011: 1.31ms 100: 2.62ms 101: 5.24ms 110: 10.5ms 111: 21.0ms |
4 | AEQ_1ST_LOCK_MODE | R/W | 0x0 | AEQ First Lock Mode This register bit controls the Adaptive Equalizer algorithm operation at initial Receiver Lock. 0: Initial AEQ lock can occur at any value 1: Initial Receiver lock restarts AEQ at 0, providing a more deterministic initial AEQ value |
3 | AEQ_RESTART | RH/W1S | 0x0 | Set high to restart AEQ adaptation from initial value. This bit is self clearing. Adaption is restarted. |
2 | SET_AEQ_FLOOR | R/W | 0x1 | AEQ adaptation starts from a pre-set floor value rather than from zero - good in long cable situations |
1:0 | RESERVED | R | 0x0 | Reserved |
AEQ_STATUS is shown in Table 5-131.
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Adaptive Equalizer Status Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | RESERVED | R | 0x0 | |
5:0 | EQ_STATUS | R | 0x0 | Adaptive EQ Status |
AEQ_BYPASS is shown in Table 5-132.
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Adaptive Equalizer Bypass Register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:5 | EQ_STAGE_1_SELECT_VALUE | R/W | 0x3 | EQ select value[5:3] - Used if adaptive EQ is bypassed. |
4 | AEQ_LOCK_MODE | R/W | 0x0 | Adaptive Equalizer lock mode When set to a 1, Receiver Lock status requires the Adaptive Equalizer to complete adaption. When set to a 0, Receiver Lock is based only on the Lock circuit itself. AEQ can not have stabilized. |
3:1 | EQ_STAGE_2_SELECT_VALUE | R/W | 0x0 | EQ select value [2:0] - Used if adaptive EQ is bypassed. |
0 | ADAPTIVE_EQ_BYPASS | R/W | 0x0 | 1: Disable adaptive EQ 0: Enable adaptive EQ |
AEQ_MIN_MAX is shown in Table 5-133.
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Adaptive Equalizer Min/Max register
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:4 | AEQ_MAX | R/W | 0xF | Adaptive Equalizer Maximum value This register sets the maximum value for the Adaptive EQ algorithm. |
3:0 | ADAPTIVE_EQ_FLOOR_VALUE | R/W | 0x8 | When AEQ floor is enabled by the SET_AEQ_FLOOR register bit (0xD2[2]), the starting setting is given by this register. |
PORT_ICR_HI is shown in Table 5-134.
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Interrupt Control High Register This register contains the upper 8 bit controls for enabling various receive port-specific interrupts.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:3 | RESERVED | R | 0x0 | Reserved |
2 | IE_FPD3_ENC_ERR | R/W | 0x0 | Interrupt on FPD-Link III Receiver Encoding Error When enabled, an interrupt is generated on detection of an encoding error on the FPD-Link III interface for the receive port as reported in the FPD3_ENC_ERROR bit in the RX_PORT_STS2 register |
1 | IE_BCC_SEQ_ERR | R/W | 0x0 | Interrupt on BCC SEQ Sequence Error When enabled, an interrupt is generated if a Sequence Error is detected for the Bidirectional Control Channel forward channel receiver as reported in the BCC_SEQ_ERROR bit in the RX_PORT_STS1 register. |
0 | IE_BCC_CRC_ERR | R/W | 0x0 | Interrupt on BCC CRC error detect When enabled, an interrupt is generated if a CRC error is detected on a Bidirectional Control Channel frame received over the FPD-Link III forward channel as reported in the BCC_CRC_ERROR bit in the RX_PORT_STS1 register. |
PORT_ICR_LO is shown in Table 5-135.
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Interrupt Control Low Register This register contains the lower 8 bit controls for enabling various receive port-specific interrupts. Interrupt status for the respective conditions are reported in the PORT_ISR_LO register.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | IE_LINE_LEN_CHG | R/W | 0x0 | Interrupt on Video Line length When enabled, an interrupt is generated if the length of the video line changes. Status is reported in the LINE_LEN_CHG bit in the RX_PORT_STS2 register. |
5 | IE_LINE_CNT_CHG | R/W | 0x0 | Interrupt on Video Line count When enabled, an interrupt is generated if the number of video lines per frame changes. Status is reported in the LINE_CNT_CHG bit in the RX_PORT_STS2 register. |
4 | IE_BUFFER_ERR | R/W | 0x0 | Interrupt on Receiver Buffer Error When enabled, an interrupt is generated if the Receive Buffer overflow is detected as reported in the BUFFER_ERROR bit in the RX_PORT_STS2 register. |
3 | RESERVED | R | 0x0 | Reserved |
2 | IE_FPD3_PAR_ERR | R/W | 0x0 | Interrupt on FPD-Link III Receiver Parity Error When enabled, an interrupt is generated on detection of parity errors on the FPD-Link III interface for the receive port. Parity error status is reported in the PARITY_ERROR bit in the RX_PORT_STS1 register. |
1 | IE_PORT_PASS | R/W | 0x0 | Interrupt on change in Port PASS status When enabled, an interrupt is generated on a change in receiver port valid status as reported in the PORT_PASS bit in the PORT_STS1 register. |
0 | IE_LOCK_STS | R/W | 0x0 | Interrupt on change in Lock Status When enabled, an interrupt is generated on a change in lock status. Status is reported in the LOCK_STS_CHG bit in the RX_PORT_STS1 register. |
PORT_ISR_HI is shown in Table 5-136.
Return to the Summary Table.
Interrupt Status High Register This register contains the upper 8 bit status of various receive port-specific interrupts.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:3 | RESERVED | R | 0x0 | Reserved |
2 | IS_FPD3_ENC_ERR | R | 0x0 | FPD-Link III Receiver Encode Error Interrupt Status An encoding error on the FPD-Link III interface for the receive port has been detected. Status is reported in the FPD3_ENC_ERROR bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register. |
1 | IS_BCC_SEQ_ERR | R | 0x0 | BCC CRC Sequence Error Interrupt Status A Sequence Error has been detected for the Bidirectional Control Channel forward channel receiver. Status is reported in the BCC_SEQ_ERROR bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register. |
0 | IS_BCC_CRC_ERR | R | 0x0 | BCC CRC error detect Interrupt Status A CRC error has been detected on a Bidirectional Control Channel frame received over the FPD-Link III forward channel. Status is reported in the BCC_CRC_ERROR bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register. |
PORT_ISR_LO is shown in Table 5-137.
Return to the Summary Table.
Interrupt Status Low Register This register contains the lower 8 bit status of various receive port-specific interrupts.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7 | RESERVED | R | 0x0 | Reserved |
6 | IS_LINE_LEN_CHG | R | 0x0 | Video Line Length Interrupt Status A change in video line length has been detected. Status is reported in the LINE_LEN_CHG bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register. |
5 | IS_LINE_CNT_CHG | R | 0x0 | Video Line Count Interrupt Status A change in number of video lines per frame has been detected. Status is reported in the LINE_CNT_CHG bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register. |
4 | IS_BUFFER_ERR | R | 0x0 | Receiver Buffer Error Interrupt Status A Receive Buffer overflow has been detected as reported in the BUFFER_ERROR bit in the RX_PORT_STS2 register. This interrupt condition is cleared by reading the RX_PORT_STS2 register. |
3 | RESERVED | R | 0x0 | Reserved |
2 | IS_FPD3_PAR_ERR | R | 0x0 | FPD-Link III Receiver Parity Error Interrupt Status A parity error on the FPD-Link III interface for the receive port has been detected. Parity error status is reported in the PARITY_ERROR bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register. |
1 | IS_PORT_PASS | R | 0x0 | Port Valid Interrupt Status A change in receiver port valid status as reported in the PORT_PASS bit in the PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register. |
0 | IS_LOCK_STS | R | 0x0 | Lock Interrupt Status A change in lock status has been detected. Status is reported in the LOCK_STS_CHG bit in the RX_PORT_STS1 register. This interrupt condition is cleared by reading the RX_PORT_STS1 register. |
FPD3_RX_ID0 is shown in Table 5-138.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FPD3_RX_ID0 | R | 0x5F | FPD3_RX_ID0: First byte ID code: '_ ' |
FPD3_RX_ID1 is shown in Table 5-139.
Return to the Summary Table.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FPD3_RX_ID1 | R | 0x55 | FPD3_RX_ID1: 2nd byte of ID code: 'U ' |
FPD3_RX_ID2 is shown in Table 5-140.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FPD3_RX_ID2 | R | 0x42 | FPD3_RX_ID2: 3rd byte of ID code: 'B ' |
FPD3_RX_ID3 is shown in Table 5-141.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FPD3_RX_ID3 | R | 0x39 | FPD3_RX_ID3: 4th byte of ID code: '9 ' |
FPD3_RX_ID4 is shown in Table 5-142.
Return to the Summary Table.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FPD3_RX_ID4 | R | 0x36 | FPD3_RX_ID4: 5th byte of ID code: '6' |
FPD3_RX_ID5 is shown in Table 5-143.
Return to the Summary Table.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:0 | FPD3_RX_ID5 | R | 0x34 | FPD3_RX_ID5: 6th byte of ID code: '4' |
I2C_RX0_ID is shown in Table 5-144.
Return to the Summary Table.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | RX_PORT0_ID | R/W | 0x0 | 7-bit Receive Port 0 I2C ID Configures the decoder for detecting transactions designated for Receiver port 0 registers. This provides a simpler method of accessing device registers specifically for port 0 without having to use the paging function to select the register page. A value of 0 in this field disables the Port0 decoder. |
0 | RESERVED | R | 0x0 | Reserved |
I2C_RX1_ID is shown in Table 5-145.
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Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | RX_PORT1_ID | R/W | 0x0 | 7-bit Receive Port 1 I2C ID Configures the decoder for detecting transactions designated for Receiver port 1 registers. This provides a simpler method of accessing device registers specifically for port 1 without having to use the paging function to select the register page. A value of 0 in this field disables the Port1 decoder. |
0 | RESERVED | R | 0x0 | Reserved |
I2C_RX2_ID is shown in Table 5-146.
Return to the Summary Table.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | RX_PORT2_ID | R/W | 0x0 | 7-bit Receive Port 2 I2C ID Configures the decoder for detecting transactions designated for Receiver port 2 registers. This provides a simpler method of accessing device registers specifically for port 2 without having to use the paging function to select the register page. A value of 0 in this field disables the Port2 decoder. |
0 | RESERVED | R | 0x0 | Reserved |
I2C_RX3_ID is shown in Table 5-147.
Return to the Summary Table.
Bit | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | RX_PORT3_ID | R/W | 0x0 | 7-bit Receive Port 3 I2C ID Configures the decoder for detecting transactions designated for Receiver port 3 registers. This provides a simpler method of accessing device registers specifically for port 3 without having to use the paging function to select the register page. A value of 0 in this field disables the Port3 decoder. |
0 | RESERVED | R | 0x0 | Reserved |