JAJSCC4A July 2016 – January 2024 DS90UB964-Q1
PRODUCTION DATA
The CSI-2 Transmitters can operate at 400Mbps, 800Mbps, or 1.6Gbps per data lane. This operation is controlled through the CSI_PLL_CTL 0x1F register.
CSI_PLL_CTL[1:0] | CSI-2 TX Data Rate | REFCLK Frequency |
---|---|---|
00 | 1.6Gbps | 25MHz |
1.472Gbps | 23MHz | |
01 | Reserved | Reserved |
10 | 800Mbps | 25MHz |
11 | 400Mbps | 25MHz |
When configuring to 800Mbps or 1.6Gbps, the CSI-2 timing parameters are automatically set based on the CSI_PLL_CTL 0x1F register. In the case of 400Mbps, the respective CSI-2 timing parameters registers must be programmed, and the appropriate override bit must be set. To enable CSI-2 400Mbps mode, set the following registers:
# Set CSI-2 Timing parameters
WriteI2C(0xB0,0x2) # set auto-increment, page 0
WriteI2C(0xB1,0x40) # CSI-2 Port 0
WriteI2C(0xB2,0x83) # TCK Prep
WriteI2C(0xB2,0x8D) # TCK Zero
WriteI2C(0xB2,0x87) # TCK Trail
WriteI2C(0xB2,0x87) # TCK Post
WriteI2C(0xB2,0x83) # THS Prep
WriteI2C(0xB2,0x86) # THS Zero
WriteI2C(0xB2,0x84) # THS Trail
WriteI2C(0xB2,0x86) # THS Exit
WriteI2C(0xB2,0x84) # TLPX
# Set CSI-2 Timing parameters
WriteI2C(0xB0,0x2) # set auto-increment, page 0
WriteI2C(0xB1,0x60) # CSI-2 Port 1
WriteI2C(0xB2,0x83) # TCK Prep
WriteI2C(0xB2,0x8D) # TCK Zero
WriteI2C(0xB2,0x87) # TCK Trail
WriteI2C(0xB2,0x87) # TCK Post
WriteI2C(0xB2,0x83) # THS Prep
WriteI2C(0xB2,0x86) # THS Zero
WriteI2C(0xB2,0x84) # THS Trail
WriteI2C(0xB2,0x86) # THS Exit
WriteI2C(0xB2,0x84) # TLPX