JAJSCC4A July   2016  – January 2024 DS90UB964-Q1

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings – JEDEC
    3. 4.3  ESD Ratings – IEC and ISO
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Thermal Information
    6. 4.6  DC Electrical Characteristics
    7. 4.7  AC Electrical Characteristics
    8. 4.8  Recommended Timing for the Serial Control Bus
    9. 4.9  AC Electrical Characteristics
    10. 4.10 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
    4. 5.4 Device Functional Modes
      1. 5.4.1  RAW Data Type Support and Rates
      2. 5.4.2  MODE Pin
      3. 5.4.3  REFCLK
      4. 5.4.4  Receiver Port Control
      5. 5.4.5  Input Jitter Tolerance
      6. 5.4.6  Adaptive Equalizer
        1. 5.4.6.1 Channel Requirements
        2. 5.4.6.2 Adaptive Equalizer Algorithm
        3. 5.4.6.3 AEQ Settings
          1. 5.4.6.3.1 AEQ Start-Up and Initialization
          2. 5.4.6.3.2 AEQ Range
          3. 5.4.6.3.3 AEQ Timing
          4. 5.4.6.3.4 AEQ Threshold
      7. 5.4.7  Channel Monitor Loop-Through Output Driver
        1. 5.4.7.1 Code Example for CMLOUT FPD3 RX Port 0:
      8. 5.4.8  RX Port Status
        1. 5.4.8.1 RX Parity Status
        2. 5.4.8.2 FPD-Link Decoder Status
        3. 5.4.8.3 RX Port Input Signal Detection
      9. 5.4.9  GPIO Support
        1. 5.4.9.1 GPIO Input Control and Status
        2. 5.4.9.2 GPIO Output Pin Control
        3. 5.4.9.3 Back Channel GPIO
        4. 5.4.9.4 GPIO Pin Status
        5. 5.4.9.5 Other GPIO Pin Controls
      10. 5.4.10 RAW Mode LV / FV Controls
      11. 5.4.11 Video Stream Forwarding
      12. 5.4.12 CSI-2 Protocol Layer
      13. 5.4.13 CSI-2 Short Packet
      14. 5.4.14 CSI-2 Long Packet
      15. 5.4.15 CSI-2 Data Identifier
      16. 5.4.16 Virtual Channel and Context
      17. 5.4.17 CSI-2 Mode Virtual Channel Mapping
        1. 5.4.17.1 Example 1
        2. 5.4.17.2 Example 2
      18. 5.4.18 CSI-2 Transmitter Frequency
      19. 5.4.19 CSI-2 Transmitter Status
      20. 5.4.20 Video Buffers
      21. 5.4.21 CSI-2 Line Count and Line Length
      22. 5.4.22 FrameSync Operation
        1. 5.4.22.1 External FrameSync Control
        2. 5.4.22.2 Internally Generated FrameSync
          1. 5.4.22.2.1 Code Example for Internally Generated FrameSync
      23. 5.4.23 CSI-2 Forwarding
        1. 5.4.23.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 5.4.23.2 Synchronized CSI-2 Forwarding
        3. 5.4.23.3 Basic Synchronized CSI-2 Forwarding
          1. 5.4.23.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 5.4.23.4 Line-Interleaved CSI-2 Forwarding
          1. 5.4.23.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 5.4.23.5 Line-Concatenated CSI-2 Forwarding
          1. 5.4.23.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 5.4.23.6 CSI-2 Replicate Mode
        7. 5.4.23.7 CSI-2 Transmitter Output Control
        8. 5.4.23.8 Enabling and Disabling CSI-2 Transmitters
    5. 5.5 Programming
      1. 5.5.1  Serial Control Bus
      2. 5.5.2  Second I2C Port
      3. 5.5.3  I2C Target Operation
      4. 5.5.4  Remote Target Operation
      5. 5.5.5  Remote Target Addressing
      6. 5.5.6  Broadcast Write to Remote Devices
        1. 5.5.6.1 Code Example for Broadcast Write
      7. 5.5.7  I2C Proxy Controller
      8. 5.5.8  I2C Proxy Controller Timing
        1. 5.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 5.5.9  Interrupt Support
        1. 5.5.9.1 Code Example to Enable Interrupts
        2. 5.5.9.2 FPD-Link III Receive Port Interrupts
        3. 5.5.9.3 Code Example to Readback Interrupts
        4. 5.5.9.4 CSI-2 Transmit Port Interrupts
      10. 5.5.10 Timestamp – Video Skew Detection
      11. 5.5.11 Pattern Generation
        1. 5.5.11.1 Reference Color Bar Pattern
        2. 5.5.11.2 Fixed Color Patterns
        3. 5.5.11.3 Pattern Generator Programming
          1. 5.5.11.3.1 Determining Color Bar Size
        4. 5.5.11.4 Code Example for Pattern Generator
      12. 5.5.12 FPD-Link BIST Mode
        1. 5.5.12.1 BIST Operation
    6. 5.6 Register Maps
      1. 5.6.1 Main_Page Registers
      2. 5.6.2 Indirect Access Registers
        1. 5.6.2.1 PATGEN_And_CSI-2 Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power-Over-Coax
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
    3. 6.3 System Examples
    4. 6.4 Power Supply Recommendations
      1. 6.4.1 VDD Power Supply
      2. 6.4.2 Power-Up Sequencing
        1. 6.4.2.1 PDB Pin
    5. 6.5 Layout
      1. 6.5.1 Layout Guidelines
        1. 6.5.1.1 Ground
        2. 6.5.1.2 Routing FPD-Link III Signal Traces and PoC Filter
        3. 6.5.1.3 CSI-2 Guidelines
      2. 6.5.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 サポート・リソース
    4. 7.4 Trademarks
    5. 7.5 静電気放電に関する注意事項
    6. 7.6 用語集
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

4.9 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERTEST CONDITIONSPIN OR FREQUENCYMINTYPMAXUNIT
HSTX DRIVER
HSTXDBRData rateCSI0_D[3:0]P/N
CSI1_D[3:0]P/N		4008001600Mbps
fCLKDDR Clock frequencyCSI0_CLKP/N
CSI1_CLKP/N		200400800MHz
ΔVCMTX(HF)Common mode voltage variations HFAbove 450MHzCSI0_D0P/N
CSI0_D1P/N
CSI0_D2P/N
CSI0_D3P/N
CSI0_CLKP/N
CSI1_D0P/N
CSI1_D1P/N
CSI1_D2P/N
CSI1_D3P/N
CSI1_CLKP/N		15mVRMS
ΔVCMTX(LF)Common mode voltage variations LFBetween 50 and 450MHz25mVRMS
tRHS
tFHS		20% to 80% Rise and Fall HSHS data rates ≤ 1Gbps (UI ≥ 1ns)0.3UI
HS data rates > 1Gbps (UI ≤ 1ns) but less than 1.5Gbps (UI ≥ 0.667ns)0.35UI
Applicable when supporting maximum HS data rates ≤ 1.5Gbps.100ps
Applicable for all HS data rates when supporting > 1.5Gbps.0.4UI
Applicable for all HS data rates when supporting > 1.5Gbps.50ps
SDDTXTX differential return lossfLPMAXHS data rates <1.5Gbps-18dB
fH-9dB
fMAX-3dB
fLPMAXHS data rates >1.5Gbps-18dB
fH-4.5dB
fMAX-2.5dB
LPTX DRIVER
tRLPRise Time LP(1)15% to 85% rise timeCSI0_D0P/N
CSI0_D1P/N
CSI0_D2P/N
CSI0_D3P/N
CSI1_D0P/N
CSI1_D1P/N
CSI1_D2P/N
CSI1_D3P/N
CSI0_CLKP/N
CSI1_CLKP/N		25ns
tFLPFall Time LP (1)15% to 85% fall time25ns
tREOTRise Time Post-EoT(1)30%-85% rise time35ns
tLP-PULSE-TXPulse width of the LP exclusive-OR clock(1)First LP exclusive-OR clock pulse after Stop state or last pulse before Stop state40ns
All other pulses20ns
tLP-PER-TXPeriod of the LP exclusive-OR clock90ns
DV/DtSRSlew rate (1)CLOAD = 0 pF500mV/ns
CLOAD = 5 pF300mV/ns
CLOAD = 20 pF250mV/ns
CLOAD = 70 pF150mV/ns
CLOAD = 0 to 70 pF (Falling Edge Only)30mV/ns
CLOAD = 0 to 70 pF (Rising Edge Only)30mV/ns
CLOAD = 0 to 70 pF (Rising Edge Only) (2)(3)30 - 0.075×(VO,INST - 700)mV/ns
CLOAD = 0 to 70 pF (Rising Edge Only) (4)(5)25 - 0.0625×(VO,INST - 500)mV/ns
CLOADLoad capacitance(1)070pF
CSI-2 TIMING SPECIFICATIONS — DATA-CLOCK TIMING (Figure 4-6, Figure 4-7)
UIINSTUI instantaneousIn 1, 2, 3, or 4 Lane Configuration
HS Data rate = 400 Mbps		CSI0_D0P/N
CSI0_D1P/N
CSI0_D2P/N
CSI0_D3P/N
CSI1_D0P/N
CSI1_D1P/N
CSI1_D2P/N
CSI1_D3P/N
CSI0_CLKP/N
CSI1_CLKP/N		2.5ns
In 1, 2, 3, or 4 Lane Configuration
HS Data rate = 800 Mbps		1.25ns
In 1, 2, 3, or 4 Lane Configuration
HS Data rate = 1.6Gbps		0.625ns
ΔUIUI variationUI ≥ 1ns (Figure 4-5)-10%10%UI
UI < 1ns (Figure 4-5)-5%5%UI
tSKEW(TX)Data to Clock Skew (measured at transmitter)
Skew between clock and data from ideal center		HS Data rate ≤ 1Gbps (Figure 4-5)-0.150.15UIINST
1Gbps ≤ HS Data rate ≤ 1.5Gbps (Figure 4-5)-0.20.2UIINST
tSKEW(TX) staticStatic Data to Clock SkewHS Data rate > 1.5Gbps-0.20.2UIINST
tSKEW(TX) dynamicDynamic Data to Clock SkewHS Data rate > 1.5Gbps-0.150.15UIINST
CSI-2 TIMING SPECIFICATIONS - GLOBAL OPERATION (Figure 4-6, Figure 4-7)
tCLK-POSTHS exit CSI0_D0P/N
CSI0_D1P/N
CSI0_D2P/N
CSI0_D3P/N
CSI1_D0P/N
CSI1_D1P/N
CSI1_D2P/N
CSI1_D3P/N
CSI0_CLKP/N
CSI1_CLKP/N		60 + 52×UIINSTns
tCLK-PRETime HS clock shall be driver prior to any associated Data Lane beginning the transition from LP to HS mode8UIINST
tCLK-PREPAREClock Lane HS Entry3895ns
tCLK-SETTLETime interval during which the HS receiver shall ignore any Clock Lane HS transitions95300ns
tCLK-TERM-ENTime-out at Clock Lane Display Module to enable HS TerminationTime for Dn to reach VTERM-EN38ns
tCLK-TRAILTime that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst 60ns
tCLK-PREPARE + tCLK-ZEROTCLK-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock 300ns
tD-TERM-ENTime for the Data Lane receiver to enable the HS line termination Time for Dn to reach V-TERM-EN35 + 4×UIINSTns
tEOTTransmitted time interval from the start of tHS-TRAIL to the start of the LP-11 state following a HS burst 105 + 12×UIINSTns
tHS-EXITTime that the transmitter drives LP=11 following a HS burst 100ns
tHS-PREPAREData Lane HS Entry 40 + 4×UIINST85 + 6×UIINSTns
tHS-PREPARE + tHS-ZEROtHS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence 145 + 10×UIINSTns
tHS-SETTLETime interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of tHS-SETTLE 85 + 6×UIINST145 + 10×UIINSTns
tHS-SKIPTime interval during which the HS-RX should ignore any transitions on the Data Lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst. 4055 + 4×UIINSTns
tHS-TRAILData Lane HS Exit 60 + 4×UIINSTns
tLPXTransmitted length of LP state 50ns
tWAKEUPRecovery Time from Ultra Low Power State (ULPS) 1ms
(1) CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be <10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2ns delay.
(2) When the output voltage is between 700 mV and 930 mV
(3) Applicable when the supported data rate ≤ 1.5Gbps
(4) When the output voltage is between 550 mV and 790 mV
(5) Applicable when the supported data rate > 1.5Gbps.
GUID-FC176185-C4B6-4097-AB19-63D3C865A5BB-low.gifFigure 4-1 LVCMOS Transition Times
GUID-FC0738FF-C4C1-4EE1-831A-882466AD26EE-low.gifFigure 4-2 FPD-Link III Receiver VID, VIN, VCM
GUID-A14DEEEE-7B4B-49D6-979D-D27F0B1FD2CA-low.gifFigure 4-3 Deserializer Data Lock Time
GUID-13334ADD-FE8D-445B-800E-A18408BC8ABF-low.gifFigure 4-4 I2C Serial Control Bus Timing
GUID-6CD216E9-A92A-4A09-8BD3-854DD228A8BB-low.gifFigure 4-5 Clock and Data Timing in HS Transmission
GUID-726C8505-78BC-47F8-AB88-AD132CE03549-low.gifFigure 4-6 Switching the Clock Lane Between Clock Transmission and Low-Power Mode
GUID-E3C97C66-56D8-4074-A27C-290B0C57EA7E-low.gifFigure 4-7 High-Speed Data Transmission Burst
GUID-486CDEF9-48AA-49A5-A693-DA5D36074645-low.gifFigure 4-8 Long Line Packets and Short Frame Sync Packets
GUID-07B689DF-98EB-470E-B22D-F1F1B55058FC-low.svgFigure 4-9 CSI-2 General Frame Format (Single Rx / VC)
GUID-29433953-5FB4-46B2-97F8-BFB464AF67CC-low.pngFigure 4-10 4 MIPI Data Lane Configuration