JAJSCC4A July   2016  – January 2024 DS90UB964-Q1

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings – JEDEC
    3. 4.3  ESD Ratings – IEC and ISO
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Thermal Information
    6. 4.6  DC Electrical Characteristics
    7. 4.7  AC Electrical Characteristics
    8. 4.8  Recommended Timing for the Serial Control Bus
    9. 4.9  AC Electrical Characteristics
    10. 4.10 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
    4. 5.4 Device Functional Modes
      1. 5.4.1  RAW Data Type Support and Rates
      2. 5.4.2  MODE Pin
      3. 5.4.3  REFCLK
      4. 5.4.4  Receiver Port Control
      5. 5.4.5  Input Jitter Tolerance
      6. 5.4.6  Adaptive Equalizer
        1. 5.4.6.1 Channel Requirements
        2. 5.4.6.2 Adaptive Equalizer Algorithm
        3. 5.4.6.3 AEQ Settings
          1. 5.4.6.3.1 AEQ Start-Up and Initialization
          2. 5.4.6.3.2 AEQ Range
          3. 5.4.6.3.3 AEQ Timing
          4. 5.4.6.3.4 AEQ Threshold
      7. 5.4.7  Channel Monitor Loop-Through Output Driver
        1. 5.4.7.1 Code Example for CMLOUT FPD3 RX Port 0:
      8. 5.4.8  RX Port Status
        1. 5.4.8.1 RX Parity Status
        2. 5.4.8.2 FPD-Link Decoder Status
        3. 5.4.8.3 RX Port Input Signal Detection
      9. 5.4.9  GPIO Support
        1. 5.4.9.1 GPIO Input Control and Status
        2. 5.4.9.2 GPIO Output Pin Control
        3. 5.4.9.3 Back Channel GPIO
        4. 5.4.9.4 GPIO Pin Status
        5. 5.4.9.5 Other GPIO Pin Controls
      10. 5.4.10 RAW Mode LV / FV Controls
      11. 5.4.11 Video Stream Forwarding
      12. 5.4.12 CSI-2 Protocol Layer
      13. 5.4.13 CSI-2 Short Packet
      14. 5.4.14 CSI-2 Long Packet
      15. 5.4.15 CSI-2 Data Identifier
      16. 5.4.16 Virtual Channel and Context
      17. 5.4.17 CSI-2 Mode Virtual Channel Mapping
        1. 5.4.17.1 Example 1
        2. 5.4.17.2 Example 2
      18. 5.4.18 CSI-2 Transmitter Frequency
      19. 5.4.19 CSI-2 Transmitter Status
      20. 5.4.20 Video Buffers
      21. 5.4.21 CSI-2 Line Count and Line Length
      22. 5.4.22 FrameSync Operation
        1. 5.4.22.1 External FrameSync Control
        2. 5.4.22.2 Internally Generated FrameSync
          1. 5.4.22.2.1 Code Example for Internally Generated FrameSync
      23. 5.4.23 CSI-2 Forwarding
        1. 5.4.23.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 5.4.23.2 Synchronized CSI-2 Forwarding
        3. 5.4.23.3 Basic Synchronized CSI-2 Forwarding
          1. 5.4.23.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 5.4.23.4 Line-Interleaved CSI-2 Forwarding
          1. 5.4.23.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 5.4.23.5 Line-Concatenated CSI-2 Forwarding
          1. 5.4.23.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 5.4.23.6 CSI-2 Replicate Mode
        7. 5.4.23.7 CSI-2 Transmitter Output Control
        8. 5.4.23.8 Enabling and Disabling CSI-2 Transmitters
    5. 5.5 Programming
      1. 5.5.1  Serial Control Bus
      2. 5.5.2  Second I2C Port
      3. 5.5.3  I2C Target Operation
      4. 5.5.4  Remote Target Operation
      5. 5.5.5  Remote Target Addressing
      6. 5.5.6  Broadcast Write to Remote Devices
        1. 5.5.6.1 Code Example for Broadcast Write
      7. 5.5.7  I2C Proxy Controller
      8. 5.5.8  I2C Proxy Controller Timing
        1. 5.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 5.5.9  Interrupt Support
        1. 5.5.9.1 Code Example to Enable Interrupts
        2. 5.5.9.2 FPD-Link III Receive Port Interrupts
        3. 5.5.9.3 Code Example to Readback Interrupts
        4. 5.5.9.4 CSI-2 Transmit Port Interrupts
      10. 5.5.10 Timestamp – Video Skew Detection
      11. 5.5.11 Pattern Generation
        1. 5.5.11.1 Reference Color Bar Pattern
        2. 5.5.11.2 Fixed Color Patterns
        3. 5.5.11.3 Pattern Generator Programming
          1. 5.5.11.3.1 Determining Color Bar Size
        4. 5.5.11.4 Code Example for Pattern Generator
      12. 5.5.12 FPD-Link BIST Mode
        1. 5.5.12.1 BIST Operation
    6. 5.6 Register Maps
      1. 5.6.1 Main_Page Registers
      2. 5.6.2 Indirect Access Registers
        1. 5.6.2.1 PATGEN_And_CSI-2 Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power-Over-Coax
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
    3. 6.3 System Examples
    4. 6.4 Power Supply Recommendations
      1. 6.4.1 VDD Power Supply
      2. 6.4.2 Power-Up Sequencing
        1. 6.4.2.1 PDB Pin
    5. 6.5 Layout
      1. 6.5.1 Layout Guidelines
        1. 6.5.1.1 Ground
        2. 6.5.1.2 Routing FPD-Link III Signal Traces and PoC Filter
        3. 6.5.1.3 CSI-2 Guidelines
      2. 6.5.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 サポート・リソース
    4. 7.4 Trademarks
    5. 7.5 静電気放電に関する注意事項
    6. 7.6 用語集
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

Layout Guidelines

Circuit board layout and stack-up for the FPD-Link III devices must be designed to provide low-noise power feed to the device. Good layout practice also separates high frequency or high-level inputs and outputs to minimize unwanted stray noise pick-up, feedback, and interference. Power system performance can be greatly improved by using thin dielectrics (2 to 4 mils) for power/ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors can include both RF ceramic and tantalum electrolytic types. RF capacitors can use values in the range of 0.01µF to 0.1µF. Ceramic capacitors can be in the 2.2µF to 10µF range. The voltage rating of the ceramic capacitors must be at least 5× the power supply voltage being used

TI recommends surface-mount capacitors due to the smaller parasitics. When using multiple capacitors per supply pin, place the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50µF to 100µF range, which smooths low frequency switching noise. TI recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor increases the inductance of the path.

A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. The small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20 to 30MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, common practice is to use two vias from power and ground pins to the planes to reduce the impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter can be used to provide clean power to sensitive circuits such as PLLs.

Use at least a four-layer board with a power and ground plane. Locate LVCMOS signals away from the differential lines to prevent coupling from the LVCMOS lines to the differential lines. Differential impedance of 100Ω are typically recommended for STP interconnect and single-ended impedance of 50Ω for coaxial interconnect. The closely coupled lines cause coupled noise to appear as common-mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.