JAJSCC4A July   2016  – January 2024 DS90UB964-Q1

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings – JEDEC
    3. 4.3  ESD Ratings – IEC and ISO
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Thermal Information
    6. 4.6  DC Electrical Characteristics
    7. 4.7  AC Electrical Characteristics
    8. 4.8  Recommended Timing for the Serial Control Bus
    9. 4.9  AC Electrical Characteristics
    10. 4.10 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
    4. 5.4 Device Functional Modes
      1. 5.4.1  RAW Data Type Support and Rates
      2. 5.4.2  MODE Pin
      3. 5.4.3  REFCLK
      4. 5.4.4  Receiver Port Control
      5. 5.4.5  Input Jitter Tolerance
      6. 5.4.6  Adaptive Equalizer
        1. 5.4.6.1 Channel Requirements
        2. 5.4.6.2 Adaptive Equalizer Algorithm
        3. 5.4.6.3 AEQ Settings
          1. 5.4.6.3.1 AEQ Start-Up and Initialization
          2. 5.4.6.3.2 AEQ Range
          3. 5.4.6.3.3 AEQ Timing
          4. 5.4.6.3.4 AEQ Threshold
      7. 5.4.7  Channel Monitor Loop-Through Output Driver
        1. 5.4.7.1 Code Example for CMLOUT FPD3 RX Port 0:
      8. 5.4.8  RX Port Status
        1. 5.4.8.1 RX Parity Status
        2. 5.4.8.2 FPD-Link Decoder Status
        3. 5.4.8.3 RX Port Input Signal Detection
      9. 5.4.9  GPIO Support
        1. 5.4.9.1 GPIO Input Control and Status
        2. 5.4.9.2 GPIO Output Pin Control
        3. 5.4.9.3 Back Channel GPIO
        4. 5.4.9.4 GPIO Pin Status
        5. 5.4.9.5 Other GPIO Pin Controls
      10. 5.4.10 RAW Mode LV / FV Controls
      11. 5.4.11 Video Stream Forwarding
      12. 5.4.12 CSI-2 Protocol Layer
      13. 5.4.13 CSI-2 Short Packet
      14. 5.4.14 CSI-2 Long Packet
      15. 5.4.15 CSI-2 Data Identifier
      16. 5.4.16 Virtual Channel and Context
      17. 5.4.17 CSI-2 Mode Virtual Channel Mapping
        1. 5.4.17.1 Example 1
        2. 5.4.17.2 Example 2
      18. 5.4.18 CSI-2 Transmitter Frequency
      19. 5.4.19 CSI-2 Transmitter Status
      20. 5.4.20 Video Buffers
      21. 5.4.21 CSI-2 Line Count and Line Length
      22. 5.4.22 FrameSync Operation
        1. 5.4.22.1 External FrameSync Control
        2. 5.4.22.2 Internally Generated FrameSync
          1. 5.4.22.2.1 Code Example for Internally Generated FrameSync
      23. 5.4.23 CSI-2 Forwarding
        1. 5.4.23.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 5.4.23.2 Synchronized CSI-2 Forwarding
        3. 5.4.23.3 Basic Synchronized CSI-2 Forwarding
          1. 5.4.23.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 5.4.23.4 Line-Interleaved CSI-2 Forwarding
          1. 5.4.23.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 5.4.23.5 Line-Concatenated CSI-2 Forwarding
          1. 5.4.23.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 5.4.23.6 CSI-2 Replicate Mode
        7. 5.4.23.7 CSI-2 Transmitter Output Control
        8. 5.4.23.8 Enabling and Disabling CSI-2 Transmitters
    5. 5.5 Programming
      1. 5.5.1  Serial Control Bus
      2. 5.5.2  Second I2C Port
      3. 5.5.3  I2C Target Operation
      4. 5.5.4  Remote Target Operation
      5. 5.5.5  Remote Target Addressing
      6. 5.5.6  Broadcast Write to Remote Devices
        1. 5.5.6.1 Code Example for Broadcast Write
      7. 5.5.7  I2C Proxy Controller
      8. 5.5.8  I2C Proxy Controller Timing
        1. 5.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 5.5.9  Interrupt Support
        1. 5.5.9.1 Code Example to Enable Interrupts
        2. 5.5.9.2 FPD-Link III Receive Port Interrupts
        3. 5.5.9.3 Code Example to Readback Interrupts
        4. 5.5.9.4 CSI-2 Transmit Port Interrupts
      10. 5.5.10 Timestamp – Video Skew Detection
      11. 5.5.11 Pattern Generation
        1. 5.5.11.1 Reference Color Bar Pattern
        2. 5.5.11.2 Fixed Color Patterns
        3. 5.5.11.3 Pattern Generator Programming
          1. 5.5.11.3.1 Determining Color Bar Size
        4. 5.5.11.4 Code Example for Pattern Generator
      12. 5.5.12 FPD-Link BIST Mode
        1. 5.5.12.1 BIST Operation
    6. 5.6 Register Maps
      1. 5.6.1 Main_Page Registers
      2. 5.6.2 Indirect Access Registers
        1. 5.6.2.1 PATGEN_And_CSI-2 Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power-Over-Coax
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
    3. 6.3 System Examples
    4. 6.4 Power Supply Recommendations
      1. 6.4.1 VDD Power Supply
      2. 6.4.2 Power-Up Sequencing
        1. 6.4.2.1 PDB Pin
    5. 6.5 Layout
      1. 6.5.1 Layout Guidelines
        1. 6.5.1.1 Ground
        2. 6.5.1.2 Routing FPD-Link III Signal Traces and PoC Filter
        3. 6.5.1.3 CSI-2 Guidelines
      2. 6.5.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 サポート・リソース
    4. 7.4 Trademarks
    5. 7.5 静電気放電に関する注意事項
    6. 7.6 用語集
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

5.5.1 Serial Control Bus

The DS90UB964-Q1 implements two I2C-compatible serial control buses. Both I2C ports support local device configuration and incorporate a bidirectional control channel (BCC) that allows communication with a remote serializers as well as remote I2C target devices.

The device address is set through a resistor divider connected to the IDx pin (R1 and R2 – see Figure 5-21).

GUID-C7BA924B-D340-4DBC-B103-715C7843EABD-low.gifFigure 5-21 Serial Control Bus Connection

The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pullup resistor to VI2C, where VI2C is a voltage rail that matches the voltage applied to VDDIO. The pull-up resistor value can be adjusted to account for capacitive loading and data rate requirements. Refer to "I2C Bus Pullup Resistor Calculation" (SLVA689) to determine the pull-up resistor value to VI2C. The signals are either pulled High, or driven Low.

The IDX pin configures the control interface to one of eight possible device addresses. A pullup resistor and a pulldown resistor can be used to set the appropriate voltage ratio between the IDX input pin (VIDX) and V(VDD18), each ratio corresponding to a specific device address. See Table 5-13, Serial Control Bus Addresses for IDX.

Table 5-13 Serial Control Bus Addresses for IDX
NO.VIDX VOLTAGE RANGEVIDX TARGET VOLTAGESUGGESTED STRAP RESISTORS (1% TOL)PRIMARY ASSIGNED I2C ADDRESS
VMINVTYPVMAXVDD18 = 1.80 VRHIGH ( kΩ )RLOW ( kΩ )7-BIT8-BIT
0000.131 × V(VDD18)0OPEN10.00x300x60
10.179 × V(VDD18)0.213 × V(VDD18)0.247 × V(VDD18)0.37488.723.20x320x64
20.296 × V(VDD18)0.330 × V(VDD18)0.362 × V(VDD18)0.58275.035.70x340x68
30.412 × V(VDD18)0.443 × V(VDD18)0.474 × V(VDD18)0.79271.556.20x360x6C
40.525 × V(VDD18)0.559 × V(VDD18)0.592 × V(VDD18)0.99578.797.60x380x70
50.642 × V(VDD18)0.673 × V(VDD18)0.704 × V(VDD18)1.20239.278.70x3A0x74
60.761 × V(VDD18)0.792 × V(VDD18)0.823 × V(VDD18)1.42025.595.30x3C0x78
70.876 × V(VDD18)V(VDD18)V(VDD18)1.810.0OPEN0x3D0x7A

The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SDA transitions Low while SCL is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See Figure 5-22.

GUID-3C971190-575E-4D72-AD3C-00E42B3AFB1E-low.gifFigure 5-22 START and STOP Conditions

To communicate with a remote device, the host controller sends the target address and listens for a response from the target. This response is referred to as an acknowledge bit (ACK). If a target on the bus is addressed correctly, the target acknowledges (ACKs) the controller by driving the SDA bus low. If the address does not match one of the target addresses of the device, the target not-acknowledges (NACKs) the controller by letting SDA be pulled High. ACKs can also occur on the bus when data transmissions are in process. When the controller is writing data, the target ACKs after every data byte is successfully received. When the controller is reading data, the controller ACKs after every data byte is received to let the target know the controller wants to receive another data byte. When the controller wants to stop reading, the controller NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 5-23 and a WRITE is shown in Figure 5-24.

GUID-FEFB2231-DB2B-4F67-B4E5-6B2D50A43796-low.svgFigure 5-23 Serial Control Bus — READ
GUID-C41E77E5-4BFA-4C84-8DD8-29219C767817-low.svgFigure 5-24 Serial Control Bus — WRITE
GUID-BD794B57-9B2F-411C-9B6D-7476D80F41AA-low.svgFigure 5-25 Basic Operation

The I2C Controller located at the Deserializer must support I2C clock stretching. For more information on I2C interface requirements and throughput considerations, refer to I2C Communication Over FPD-Link III With Bidirectional Control Channel (SNLA131) and I2C over DS90UB913/4 FPD-Link III With Bidirectional Control Channel (SNLA222).