JAJSCG7 September   2016 LMK04208

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Charge Pump Current Specification Definitions
      1. 7.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage
      2. 7.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch
      3. 7.1.3 Charge Pump Output Current Magnitude Variation vs. Ambient Temperature
    2. 7.2 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1  System Architecture
      2. 8.1.2  PLL1 Redundant Reference Inputs (CLKin0/CLKin0* and CLKin1/CLKin1*)
      3. 8.1.3  PLL1 Tunable Crystal Support
      4. 8.1.4  VCXO/Crystal Buffered Output
      5. 8.1.5  Frequency Holdover
      6. 8.1.6  Integrated Loop Filter Poles
      7. 8.1.7  Internal VCO
      8. 8.1.8  External VCO Mode
      9. 8.1.9  Clock Distribution
        1. 8.1.9.1 CLKout DIVIDER
        2. 8.1.9.2 CLKout Delay
        3. 8.1.9.3 Programmable Output Type
        4. 8.1.9.4 Clock Output Synchronization
      10. 8.1.10 0-Delay
      11. 8.1.11 Default Startup Clocks
      12. 8.1.12 Status Pins
      13. 8.1.13 Register Readback
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Inputs / Outputs
        1. 8.3.1.1 PLL1 Reference Inputs (CLKin0 and CLKin1)
        2. 8.3.1.2 PLL2 OSCin / OSCin* Port
        3. 8.3.1.3 Crystal Oscillator
      2. 8.3.2 Input Clock Switching
        1. 8.3.2.1 Input Clock Switching - Manual Mode
        2. 8.3.2.2 Input Clock Switching - Pin Select Mode
          1. 8.3.2.2.1 Pin Select Mode and Host
          2. 8.3.2.2.2 Switch Event without Holdover
          3. 8.3.2.2.3 Switch Event with Holdover
        3. 8.3.2.3 Input Clock Switching - Automatic Mode
          1. 8.3.2.3.1 Starting Active Clock
          2. 8.3.2.3.2 Clock Switch Event: PLL1 DLD
          3. 8.3.2.3.3 Clock Switch Event: PLL1 Vtune Rail
          4. 8.3.2.3.4 Clock Switch Event with Holdover
        4. 8.3.2.4 Input Clock Switching - Automatic Mode with Pin Select
          1. 8.3.2.4.1 Starting Active Clock
          2. 8.3.2.4.2 Clock Switch Event: PLL1 DLD
          3. 8.3.2.4.3 Clock Switch Event: PLL1 Vtune Rail
          4. 8.3.2.4.4 Clock Switch Event with Holdover
      3. 8.3.3 Holdover Mode
        1. 8.3.3.1 Enable Holdover
        2. 8.3.3.2 Entering Holdover
        3. 8.3.3.3 During Holdover
        4. 8.3.3.4 Exiting Holdover
        5. 8.3.3.5 Holdover Frequency Accuracy and DAC Performance
        6. 8.3.3.6 Holdover Mode - Automatic Exit of Holdover
      4. 8.3.4 PLLs
        1. 8.3.4.1 PLL1
        2. 8.3.4.2 PLL2
          1. 8.3.4.2.1 PLL2 Frequency Doubler
        3. 8.3.4.3 Digital Lock Detect
      5. 8.3.5 Status Pins
        1. 8.3.5.1 Logic Low
        2. 8.3.5.2 Digital Lock Detect
        3. 8.3.5.3 Holdover Status
        4. 8.3.5.4 DAC
        5. 8.3.5.5 PLL Divider Outputs
        6. 8.3.5.6 CLKinX_LOS
        7. 8.3.5.7 CLKinX Selected
        8. 8.3.5.8 MICROWIRE Readback
      6. 8.3.6 VCO
      7. 8.3.7 Clock Distribution
        1. 8.3.7.1 Fixed Digital Delay
        2. 8.3.7.2 Fixed Digital Delay - Example
        3. 8.3.7.3 Clock Output Synchronization (SYNC)
          1. 8.3.7.3.1 Effect of SYNC
          2. 8.3.7.3.2 Methods of Generating SYNC
          3. 8.3.7.3.3 Avoiding Clock Output Interruption Due to Sync
          4. 8.3.7.3.4 SYNC Timing
        4. 8.3.7.4 Dynamically Programming Digital Delay
          1. 8.3.7.4.1 Absolute vs. Relative Dynamic Digital Delay
          2. 8.3.7.4.2 Dynamic Digital Delay and 0-Delay Mode
          3. 8.3.7.4.3 SYNC and Minimum Step Size
          4. 8.3.7.4.4 Programming Overview
          5. 8.3.7.4.5 Internal Dynamic Digital Delay Timing
          6. 8.3.7.4.6 Other Timing Requirements
        5. 8.3.7.5 Absolute Dynamic Digital Delay
          1. 8.3.7.5.1 Absolute Dynamic Digital Delay - Example
        6. 8.3.7.6 Relative Dynamic Digital Delay
          1. 8.3.7.6.1 Relative Dynamic Digital Delay - Example
      8. 8.3.8 0-Delay Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mode Selection
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Dual PLL
        2. 8.4.2.2 0-Delay Dual PLL
        3. 8.4.2.3 Single PLL
        4. 8.4.2.4 0-Delay Single PLL
        5. 8.4.2.5 Clock Distribution
    5. 8.5 Programming
      1. 8.5.1 Special Programming Case for R0 to R5 for CLKoutX_DIV and CLKoutX_DDLY
        1. 8.5.1.1 Example
      2. 8.5.2 Recommended Programming Sequence
        1. 8.5.2.1 Programming Sequence Overview
      3. 8.5.3 Readback
        1. 8.5.3.1 Readback - Example
    6. 8.6 Register Maps
      1. 8.6.1 Register Map and Readback Register Map
      2. 8.6.2 Default Device Register Settings After Power On Reset
      3. 8.6.3 Register Descriptions
        1. 8.6.3.1  Registers R0 to R5
          1. 8.6.3.1.1 CLKoutX_PD, Powerdown CLKoutX Output Path
          2. 8.6.3.1.2 CLKoutX_OSCin_Sel, Clock Group Source
          3. 8.6.3.1.3 CLKoutX_ADLY_SEL, Select Analog Delay
          4. 8.6.3.1.4 CLKoutX_DDLY, Clock Channel Digital Delay
          5. 8.6.3.1.5 Reset
          6. 8.6.3.1.6 POWERDOWN
          7. 8.6.3.1.7 CLKoutX_HS, Digital Delay Half Shift
          8. 8.6.3.1.8 CLKoutX_DIV, Clock Output Divide
        2. 8.6.3.2  Registers R6 to R8
          1. 8.6.3.2.1 CLKoutX_TYPE
          2. 8.6.3.2.2 CLKoutX_ADLY
        3. 8.6.3.3  Register R10
          1. 8.6.3.3.1 OSCout_TYPE
          2. 8.6.3.3.2 EN_OSCout, OSCout Output Enable
          3. 8.6.3.3.3 OSCout_MUX, Clock Output Mux
          4. 8.6.3.3.4 PD_OSCin, OSCin Powerdown Control
          5. 8.6.3.3.5 OSCout_DIV, Oscillator Output Divide
          6. 8.6.3.3.6 VCO_MUX
          7. 8.6.3.3.7 EN_FEEDBACK_MUX
          8. 8.6.3.3.8 VCO_DIV, VCO Divider
          9. 8.6.3.3.9 FEEDBACK_MUX
        4. 8.6.3.4  Register R11
          1. 8.6.3.4.1 MODE: Device Mode
          2. 8.6.3.4.2 EN_SYNC, Enable Synchronization
          3. 8.6.3.4.3 NO_SYNC_CLKoutX
          4. 8.6.3.4.4 SYNC_MUX
          5. 8.6.3.4.5 SYNC_QUAL
          6. 8.6.3.4.6 SYNC_POL_INV
          7. 8.6.3.4.7 SYNC_EN_AUTO
          8. 8.6.3.4.8 SYNC_TYPE
          9. 8.6.3.4.9 EN_PLL2_XTAL
        5. 8.6.3.5  Register R12
          1. 8.6.3.5.1 LD_MUX
          2. 8.6.3.5.2 LD_TYPE
          3. 8.6.3.5.3 SYNC_PLLX_DLD
          4. 8.6.3.5.4 EN_TRACK
          5. 8.6.3.5.5 HOLDOVER_MODE
        6. 8.6.3.6  Register R13
          1. 8.6.3.6.1 HOLDOVER_MUX
          2. 8.6.3.6.2 HOLDOVER_TYPE
          3. 8.6.3.6.3 Status_CLKin1_MUX
          4. 8.6.3.6.4 Status_CLKin0_TYPE
          5. 8.6.3.6.5 DISABLE_DLD1_DET
          6. 8.6.3.6.6 Status_CLKin0_MUX
          7. 8.6.3.6.7 CLKin_SELECT_MODE
          8. 8.6.3.6.8 CLKin_Sel_INV
          9. 8.6.3.6.9 EN_CLKinX
        7. 8.6.3.7  Register 14
          1. 8.6.3.7.1 LOS_TIMEOUT
          2. 8.6.3.7.2 EN_LOS
          3. 8.6.3.7.3 Status_CLKin1_TYPE
          4. 8.6.3.7.4 CLKinX_BUF_TYPE, PLL1 CLKinX/CLKinX* Buffer Type
          5. 8.6.3.7.5 DAC_HIGH_TRIP
          6. 8.6.3.7.6 DAC_LOW_TRIP
          7. 8.6.3.7.7 EN_VTUNE_RAIL_DET
        8. 8.6.3.8  Register 15
          1. 8.6.3.8.1 MAN_DAC
          2. 8.6.3.8.2 EN_MAN_DAC
          3. 8.6.3.8.3 HOLDOVER_DLD_CNT
          4. 8.6.3.8.4 FORCE_HOLDOVER
        9. 8.6.3.9  Register 16
          1. 8.6.3.9.1 XTAL_LVL
        10. 8.6.3.10 Register 23
          1. 8.6.3.10.1 DAC_CNT
        11. 8.6.3.11 Register 24
          1. 8.6.3.11.1 PLL2_C4_LF, PLL2 Integrated Loop Filter Component
          2. 8.6.3.11.2 PLL2_C3_LF, PLL2 Integrated Loop Filter Component
          3. 8.6.3.11.3 PLL2_R4_LF, PLL2 Integrated Loop Filter Component
          4. 8.6.3.11.4 PLL2_R3_LF, PLL2 Integrated Loop Filter Component
          5. 8.6.3.11.5 PLL1_N_DLY
          6. 8.6.3.11.6 PLL1_R_DLY
          7. 8.6.3.11.7 PLL1_WND_SIZE
        12. 8.6.3.12 Register 25
          1. 8.6.3.12.1 DAC_CLK_DIV
          2. 8.6.3.12.2 PLL1_DLD_CNT
        13. 8.6.3.13 Register 26
          1. 8.6.3.13.1 PLL2_WND_SIZE
          2. 8.6.3.13.2 EN_PLL2_REF_2X, PLL2 Reference Frequency Doubler
          3. 8.6.3.13.3 PLL2_CP_POL, PLL2 Charge Pump Polarity
          4. 8.6.3.13.4 PLL2_CP_GAIN, PLL2 Charge Pump Current
          5. 8.6.3.13.5 PLL2_DLD_CNT
          6. 8.6.3.13.6 PLL2_CP_TRI, PLL2 Charge Pump TRI-STATE
        14. 8.6.3.14 Register 27
          1. 8.6.3.14.1 PLL1_CP_POL, PLL1 Charge Pump Polarity
          2. 8.6.3.14.2 PLL1_CP_GAIN, PLL1 Charge Pump Current
          3. 8.6.3.14.3 CLKinX_PreR_DIV
          4. 8.6.3.14.4 PLL1_R, PLL1 R Divider
          5. 8.6.3.14.5 PLL1_CP_TRI, PLL1 Charge Pump TRI-STATE
        15. 8.6.3.15 Register 28
          1. 8.6.3.15.1 PLL2_R, PLL2 R Divider
          2. 8.6.3.15.2 PLL1_N, PLL1 N Divider
        16. 8.6.3.16 Register 29
          1. 8.6.3.16.1 OSCin_FREQ, PLL2 Oscillator Input Frequency Register
          2. 8.6.3.16.2 PLL2_FAST_PDF, High PLL2 Phase Detector Frequency
          3. 8.6.3.16.3 PLL2_N_CAL, PLL2 N Calibration Divider
        17. 8.6.3.17 Register 30
          1. 8.6.3.17.1 PLL2_P, PLL2 N Prescaler Divider
          2. 8.6.3.17.2 PLL2_N, PLL2 N Divider
        18. 8.6.3.18 Register 31
          1. 8.6.3.18.1 READBACK_LE
          2. 8.6.3.18.2 READBACK_ADDR
          3. 8.6.3.18.3 uWire_LOCK
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Loop Filter
        1. 9.1.1.1 PLL1
        2. 9.1.1.2 PLL2
      2. 9.1.2 Driving CLKin and OSCin Inputs
        1. 9.1.2.1 Driving CLKin Pins with a Differential Source
        2. 9.1.2.2 Driving CLKin Pins with a Single-Ended Source
      3. 9.1.3 Termination and Use of Clock Output (Drivers)
        1. 9.1.3.1 Termination for DC Coupled Differential Operation
        2. 9.1.3.2 Termination for AC Coupled Differential Operation
        3. 9.1.3.3 Termination for Single-Ended Operation
      4. 9.1.4 Frequency Planning with the LMK04208
      5. 9.1.5 PLL Programming
        1. 9.1.5.1 Example PLL2 N Divider Programming
      6. 9.1.6 Digital Lock Detect Frequency Accuracy
        1. 9.1.6.1 Minimum Lock Time Calculation Example
      7. 9.1.7 Calculating Dynamic Digital Delay Values for Any Divide
        1. 9.1.7.1 Example
      8. 9.1.8 Optional Crystal Oscillator Implementation (OSCin/OSCin*)
        1. 9.1.8.1 Examples of Phase Noise and Jitter Performance
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
          1. 9.2.2.1.1 Clock Architect
          2. 9.2.2.1.2 Calculation Using LCM
        2. 9.2.2.2 Device Configuration
          1. 9.2.2.2.1 PLL LO Reference
          2. 9.2.2.2.2 POR Clock
        3. 9.2.2.3 PLL Loop Filter Design
          1. 9.2.2.3.1 PLL1 Loop Filter Design
          2. 9.2.2.3.2 PLL2 Loop Filter Design
        4. 9.2.2.4 Clock Output Assignment
        5. 9.2.2.5 Other Device Specific Configuration
          1. 9.2.2.5.1 Digital Lock Detect
          2. 9.2.2.5.2 Holdover
        6. 9.2.2.6 Device Programming
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 System Level Diagram
    4. 9.4 Do's and Don'ts
      1. 9.4.1 LVCMOS Complementary vs. Non-Complementary Operation
      2. 9.4.2 LVPECL Outputs
      3. 9.4.3 Sharing MICROWIRE (SPI) Lines
  10. 10Power Supply Recommendations
    1. 10.1 Pin Connection Recommendations
      1. 10.1.1 Vcc Pins and Decoupling
        1. 10.1.1.1 Vcc2, Vcc3, Vcc10, Vcc11, Vcc12, Vcc13 (CLKout Vccs)
        2. 10.1.1.2 Vcc1 (VCO), Vcc4 (Digital), and Vcc9 (PLL2)
        3. 10.1.1.3 Vcc6 (PLL1 Charge Pump) and Vcc8 (PLL2 Charge Pump)
        4. 10.1.1.4 Vcc5 (CLKin), Vcc7 (OSCin and OSCout)
      2. 10.1.2 LVPECL Outputs
      3. 10.1.3 Unused Clock Outputs
      4. 10.1.4 Unused Clock Inputs
      5. 10.1.5 LDO Bypass
    2. 10.2 Current Consumption and Power Dissipation Calculations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(3)(1)
MIN MAX UNIT
VCC Supply voltage (2) –0.3 3.6 V
VIN Input voltage –0.3 VCC + 0.3 V
TL Lead temperature (solder 4 seconds) 260 °C
TJ Junction temperature 150 °C
IIN Differential input current (CLKinX/X*,
OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*)		 ± 5 mA
MSL Moisture Sensitivity Level 3
Tstg Storage temperature -65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Never to exceed 3.6 V.
(3) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
TJ Junction temperature 125 °C
TA Ambient temperature VCC = 3.3 V –40 25 85 °C
VCC Supply voltage 3.15 3.3 3.45 V

6.4 Thermal Information

THERMAL METRIC(1) LMK04208 UNIT
NKD (WQFN)
64 PINS
RθJA Junction-to-ambient thermal resistance on 4-layer JEDEC PCB(2)(8) 25.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(3)(9) 6.9 °C/W
RθJB Junction-to-board thermal resistance(4) 4.0 °C/W
ψJT Junction-to-top characterization parameter(5) 0.1 °C/W
ψJB Junction-to-board characterization parameter(6) 4.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance(7) 0.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(8) Specification assumes 32 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC PCB. These vias play a key role in improving the thermal performance of the WQFN. Note that the JEDEC PCB is a standard thermal measurement PCB and does not represent best performance a PCB can achieve. TI recommends that the maximum number of vias be used in the board layout. R θJA is unique for each PCB.
(9) Case is defined as the DAP (die attach pad)

6.5 Electrical Characteristics

3.15 V ≤ VCC ≤ 3.45 V, –40 °C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C, at the Recommended Operating Conditions at the time of product characterization and are not specified.(4)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
ICC_PD Power down supply current 1 3 mA
ICC_CLKS Supply current with all clocks (CLKoutX) and OSCout enabled as LVDS.(2) All clock delays disabled,
CLKoutX_DIV = 1045,
EN_SYNC=0
PLL1 and PLL2 locked.		 445 535 mA
CLKin0/0* and CLKin1/1* INPUT CLOCK SPECIFICATIONS
fCLKin Clock input frequency(3) 0.001 500 MHz
SLEWCLKin(4) Clock input slew rate(17) 20% to 80% 0.15 0.5 V/ns
VIDCLKin Clock input
Differential input voltage (see (1) and Figure 8)		 AC coupled
CLKinX_BUF_TYPE = 0 (Bipolar)		 0.25 1.55 |V|
VSSCLKin 0.5 3.1 Vpp
VIDCLKin AC coupled
CLKinX_BUF_TYPE = 1 (MOS)		 0.25 1.55 |V|
VSSCLKin 0.5 3.1 Vpp
VCLKin Clock input
Single-ended input voltage(17)		 AC coupled to CLKinX; CLKinX* AC coupled to Ground
CLKinX_BUF_TYPE = 0 (Bipolar)		 0.25 2.4 Vpp
AC coupled to CLKinX; CLKinX* AC coupled to Ground
CLKinX_BUF_TYPE = 1 (MOS)		 0.25 2.4 Vpp
VCLKin0-offset DC offset voltage between CLKin0/CLKin0*
CLKin0* - CLKin0		 Each pin AC coupled
CLKin0_BUF_TYPE = 0 (Bipolar)		 20 mV
VCLKin1-offset DC offset voltage between CLKin1/CLKin1*
CLKin1* - CLKin1		 0 mV
VCLKinX-offset DC offset voltage between CLKinX/CLKinX*
CLKinX* - CLKinX		 Each pin AC coupled
CLKinX_BUF_TYPE = 1 (MOS)		 55 mV
VCLKin- VIH High input voltage DC coupled to CLKinX; CLKinX* AC coupled to Ground
CLKinX_BUF_TYPE = 1 (MOS)		 2.0 VCC V
VCLKin- VIL Low input voltage 0.0 0.4 V
FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS
fFBCLKin Clock input frequency(17) AC coupled
(CLKinX_BUF_TYPE = 0)
MODE = 2 or 8; FEEDBACK_MUX = 6		 0.001 1000 MHz
fFin Clock input frequency(17) AC coupled
(CLKinX_BUF_TYPE = 0)
MODE = 3 or 11		 0.001 3100 MHz
VFBCLKin/Fin Single Ended
Clock input voltage(17)		 AC coupled;
(CLKinX_BUF_TYPE = 0)		 0.25 2.0 Vpp
SLEWFBCLKin/Fin Slew rate on CLKin(17)(4) AC coupled; 20% to 80%;
(CLKinX_BUF_TYPE = 0)		 0.15 0.5 V/ns
PLL1 SPECIFICATIONS
fPD1 PLL1 phase detector frequency 40 MHz
ICPout1SOURCE PLL1 charge
Pump source current(5)		 VCPout1 = VCC/2, PLL1_CP_GAIN = 0 100 µA
VCPout1 = VCC/2, PLL1_CP_GAIN = 1 200
VCPout1 = VCC/2, PLL1_CP_GAIN = 2 400
VCPout1 = VCC/2, PLL1_CP_GAIN = 3 1600
ICPout1SINK PLL1 charge
Pump sink current(5)		 VCPout1=VCC/2, PLL1_CP_GAIN = 0 –100 µA
VCPout1=VCC/2, PLL1_CP_GAIN = 1 –200
VCPout1=VCC/2, PLL1_CP_GAIN = 2 –400
VCPout1=VCC/2, PLL1_CP_GAIN = 3 –1600
ICPout1%MIS Charge pump
Sink/source mismatch		 VCPout1 = VCC/2, T = 25 °C 3% 10%
ICPout1VTUNE Magnitude of charge pump current variation vs. charge pump voltage 0.5 V < VCPout1 < VCC - 0.5 V
TA = 25 °C		 4%
ICPout1%TEMP Charge pump current vs.
temperature variation		 4%
ICPout1 TRI Charge Pump TRI-STATE leakage current 0.5 V < VCPout < VCC - 0.5 V 5 nA
PN10kHz PLL 1/f noise at 10 kHz offset.(9) Normalized to 1 GHz Output Frequency PLL1_CP_GAIN = 400 µA –117 dBc/Hz
PLL1_CP_GAIN = 1600 µA –118
PN1Hz Normalized phase noise contribution(10) PLL1_CP_GAIN = 400 µA –221.5 dBc/Hz
PLL1_CP_GAIN = 1600 µA –223
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS
fOSCin PLL2 reference input(6) 500 MHz
SLEWOSCin PLL2 reference clock minimum slew rate on OSCin(17) 20% to 80% 0.15 0.5 V/ns
VOSCin Input voltage for OSCin or OSCin*(17) AC coupled; Single-ended (Unused pin AC coupled to GND) 0.2 2.4 Vpp
VIDOSCin Differential voltage swing (see Figure 8) AC coupled 0.2 1.55 |V|
VSSOSCin 0.4 3.1 Vpp
VOSCin-offset DC offset voltage between OSCin/OSCin*
OSCinX* - OSCinX		 Each pin AC coupled 20 mV
fdoubler_max Doubler input frequency(17) EN_PLL2_REF_2X = 1;(7)
OSCin Duty Cycle 40% to 60%		 155 MHz
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
fXTAL Crystal frequency range(17) RESR < 40 Ω 6 20.5 MHz
PXTAL Crystal power dissipation(8) Vectron VXB1 crystal, 20.48 MHz, RESR < 40 Ω
XTAL_LVL = 0		 100 µW
CIN Input capacitance of
LMK04208 OSCin port		 -40 to +85 °C 6 pF
PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS
fPD2 Phase detector frequency 155 MHz
ICPoutSOURCE PLL2 charge pump source current(5) VCPout2=VCC/2, PLL2_CP_GAIN = 0 100 µA
VCPout2=VCC/2, PLL2_CP_GAIN = 1 400
VCPout2=VCC/2, PLL2_CP_GAIN = 2 1600
VCPout2=VCC/2, PLL2_CP_GAIN = 3 3200
ICPoutSINK PLL2 charge pump sink current(5) VCPout2=VCC/2, PLL2_CP_GAIN = 0 –100 µA
VCPout2=VCC/2, PLL2_CP_GAIN = 1 –400
VCPout2=VCC/2, PLL2_CP_GAIN = 2 –1600
VCPout2=VCC/2, PLL2_CP_GAIN = 3 –3200
ICPout2%MIS Charge pump sink/source mismatch VCPout2=VCC/2, TA = 25 °C 3% 10%
ICPout2VTUNE Magnitude of charge pump current vs. charge pump voltage variation 0.5 V < VCPout2 < VCC - 0.5 V
TA = 25 °C		 4%
ICPout2%TEMP Charge pump current vs.
Temperature variation		 4%
ICPout2TRI Charge pump leakage 0.5 V < VCPout2 < VCC - 0.5 V 10 nA
PN10kHz PLL 1/f Noise at 10 kHz offset(9)
Normalized to 1 GHz output frequency		 PLL2_CP_GAIN = 400 µA –118 dBc/Hz
PLL2_CP_GAIN = 3200 µA –121
PN1Hz Normalized Phase Noise Contribution(10) PLL2_CP_GAIN = 400 µA –222.5 dBc/Hz
PLL2_CP_GAIN = 3200 µA –227
INTERNAL VCO SPECIFICATIONS
fVCO VCO tuning range LMK04208 2750 3072 MHz
KVCO Fine tuning sensitivity
(The range displayed in the typical column indicates the lower sensitivity is typical at the lower end of the tuning range, and the higher tuning sensitivity is typical at the higher end of the tuning range).		 LMK04208 20 to 36 MHz/V
|ΔTCL| Allowable Temperature Drift for Continuous Lock(11) (17) After programming R30 for lock, no changes to output configuration are permitted to ensure continuous lock 125 °C
CLKout CLOSED LOOP JITTER SPECIFICATIONS USING a COMMERCIAL QUALITY VCXO(14)
L(f)CLKout LMK04208
fCLKout = 245.76 MHz
SSB Phase noise
Measured at clock outputs
Value is average for all output types(12)		 Offset = 1 kHz –122.5 dBc/Hz
Offset = 10 kHz –132.9
Offset = 100 kHz –135.2
Offset = 800 kHz –143.9
Offset = 10 MHz; LVDS –156.0
Offset = 10 MHz; LVPECL 1600 mVpp –157.5
Offset = 10 MHz; LVCMOS –157.1
JCLKout
LVDS/LVPECL/LVCMOS		 LMK04208(12)
fCLKout = 245.76 MHz
Integrated RMS jitter
 BW = 12 kHz to 20 MHz 111 fs, RMS
BW = 100 Hz to 20 MHz 123
CLKout CLOSED LOOP JITTER SPECIFICATIONS USING THE INTEGRATED LOW NOISE CRYSTAL OSCILLATOR CIRCUIT (15)
LMK04208
fCLKout = 245.76 MHz
Integrated RMS jitter		 BW = 12 kHz to 20 MHz
XTAL_LVL = 3		 192 fs rms
BW = 100 Hz to 20 MHz
XTAL_LVL = 3		 450
DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY
fCLKout-startup Default output clock frequency at device power on(16) CLKout4, LVDS, LMK04208 90 110 130 MHz
CLOCK SKEW and DELAY
|TSKEW| Maximum CLKoutX to CLKoutY(17)(13) LVDS-to-LVDS, T = 25 °C,
FCLK = 800 MHz, RL= 100 Ω
AC coupled		 30 ps
LVPECL-to-LVPECL,
T = 25 °C,
FCLK = 800 MHz, RL= 100 Ω
emitter resistors =
240 Ω to GND
AC coupled		 30
Maximum skew between any two LVCMOS outputs, same CLKout or different CLKout(17)(13) RL = 50 Ω, CL = 5 pF,
T = 25 °C, FCLK = 100 MHz.		 100
MixedTSKEW LVDS or LVPECL to LVCMOS Same device, T = 25 °C,
250 MHz		 750 ps
td0-DELAY CLKin to CLKoutX delay(13) MODE = 2
PLL1_R_DLY = 0; PLL1_N_DLY = 0		 1850 ps
MODE = 2
PLL1_R_DLY = 0; PLL1_N_DLY = 0;
VCO Frequency = 2949.12 MHz
Analog delay select = 0;
Feedback clock digital delay = 11;
Feedback clock half step = 1;
Output clock digital delay = 5;
Output clock half step = 0;
 0
LVDS CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 1
fCLKout Maximum frequency(17)(18) RL = 100 Ω 1536 MHz
VOD Differential output voltage (see Figure 9) T = 25 °C, DC measurement
AC coupled to receiver input
R = 100-Ω differential termination		 250 400 450 |mV|
VSS 500 800 900 mVpp
ΔVOD Change in magnitude of VOD for complementary output states –50 50 mV
VOS Output offset voltage 1.125 1.25 1.375 V
ΔVOS Change in VOS for complementary output states 35 |mV|
TR / TF Output rise time 20% to 80%, RL = 100 Ω 200 ps
Output fall time 80% to 20%, RL = 100 Ω
ISA
ISB		 Output short circuit current
single-ended		 Single-ended output shorted to GND
T = 25 °C		 –24 24 mA
ISAB Output short circuit current - differential Complimentary outputs tied together –12 12 mA
LVPECL CLOCK OUTPUTS (CLKoutX)
fCLKout Maximum frequency(17)(18) 1536 MHz
TR / TF 20% to 80% output rise RL = 100 Ω, emitter resistors = 240 Ω to GND
CLKoutX_TYPE = 4 or 5
(1600 or 2000 mVpp)		 150 ps
80% to 20% output fall time
700-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 2
VOH Output high voltage T = 25 °C, DC measurement
Termination = 50 Ω to
VCC - 1.4 V		 VCC – 1.03 V
VOL Output low voltage VCC – 1.41 V
VOD Output voltage (see Figure 9) 305 380 440 |mV|
VSS 610 760 880 mVpp
1200-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 3
VOH Output high voltage T = 25 °C, DC measurement
Termination = 50 Ω to
VCC - 1.7 V		 VCC – 1.07 V
VOL Output low voltage VCC – 1.69 V
VOD Output voltage (see Figure 9) 545 625 705 |mV|
VSS 1090 1250 1410 mVpp
1600-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 4
VOH Output high voltage T = 25 °C, DC Measurement
Termination = 50 Ω to
VCC - 2.0 V		 VCC – 1.10 V
VOL Output low voltage VCC – 1.97 V
VOD Output voltage (see Figure 9) 660 870 965 |mV|
VSS 1320 1740 1930 mVpp
2000-mVpp LVPECL (2VPECL) CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 5
VOH Output high voltage T = 25 °C, DC Measurement
Termination = 50 Ω to
VCC - 2.3 V 		VCC – 1.13 V
VOL Output low voltage VCC – 2.20 V
VOD Output voltage Figure 9 800 1070 1200 |mV|
VSS 1600 2140 2400 mVpp
LVCMOS CLOCK OUTPUTS (CLKoutX)
fCLKout Maximum frequency(17)(18) 5 pF Load 250 MHz
VOH Output high voltage 1 mA Load VCC – 0.1 V
VOL Output low voltage 1 mA Load 0.1 V
IOH Output high current (source) VCC = 3.3 V, VO = 1.65 V 28 mA
IOL Output low current (sink) VCC = 3.3 V, VO = 1.65 V 28 mA
DUTYCLK Output duty cycle(17) VCC/2 to VCC/2, FCLK = 100 MHz
T = 25 °C 		45% 50% 55%
TR Output rise time 20% to 80%, RL = 50 Ω,
CL = 5 pF		 400 ps
TF Output fall time 80% to 20%, RL = 50 Ω,
CL = 5 pF		 400 ps
DIGITAL OUTPUTS (Status_CLKinX, Status_LD, Status_Holdover, SYNC)
VOH High-level output voltage IOH = -500 µA VCC – 0.4 V
VOL Low-level output voltage IOL = 500 µA 0.4 V
DIGITAL INPUTS (Status_CLKinX, SYNC)
VIH High-level input voltage 1.6 VCC V
VIL Low-level input voltage 0.4 V
IIH High-level input current
VIH = VCC		 Status_CLKinX_TYPE = 0
(High Impedance)		 –5 5 µA
Status_CLKinX_TYPE = 1
(Pull-up)		 –5 5
Status_CLKinX_TYPE = 2
(Pull-down)		 10 80
IIL Low-level input current
VIL = 0 V		 Status_CLKinX_TYPE = 0
(High Impedance)		 –5 5 µA
Status_CLKinX_TYPE = 1
(Pull-up)		 –40 -5
Status_CLKinX_TYPE = 2
(Pull-down)		 –5 5
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire)
VIH High-level input voltage 1.6 VCC V
VIL Low-level input voltage 0.4 V
IIH High-level input current VIH = VCC 5 25 µA
IIL Low-level input current VIL = 0 –5 5 µA
(1) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
(2) Load conditions for output clocks: LVDS: 100 Ω differential. See Current Consumption and Power Dissipation Calculations for Icc for specific part configuration and how to calculate Icc for a specific design.
(3) CLKin0, CLKin1 maximum is specified by characterization, production tested at 200 MHz.
(4) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance begins to degrade as the clock input slew rate is reduced. However, the device functions at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) are less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.
(5) This parameter is programmable
(6) FOSCin maximum frequency specified by characterization. Production tested at 200 MHz.
(7) The EN_PLL2_REF_2X bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path.
(8) See Application Section discussion of Optional Crystal Oscillator Implementation (OSCin/OSCin*).
(9) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f).
(10) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat(f) - 20log(N) - 10log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
(11) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R30 register was last programmed, and still have the part stay in lock. The action of programming the R30 register, even to the same value, activates a frequency calibration routine. This implies the part works over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it is necessary to reload the R30 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of -40 °C to 85 °C without violating specifications.
(12) fVCO = 2949.12 MHz, PLL1 parameters: FPD1 = 1.024 MHz, ICP1 = 100 μA, loop bandwidth = 10 Hz. 122.88 MHz Crystek CVHD-950–122.880. PLL2 parameters: PLL2_R = 1, FPD2 = 122.88 MHz, ICP2 = 3200 μA, C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, PLL2_C3_LF = 0, PLL2_R3_LF = 0, PLL2_C4_LF = 0, PLL2_R4_LF = 0, CLKoutX_DIV = 12, and CLKoutX_ADLY_SEL = 0.
(13) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification is not valid for CLKoutX or CLKoutY in analog delay mode.
(14) VCXO used is a 122.88-MHz Crystek CVHD-950-122.880.
(15) Crystal used is a 20.48-MHz Vectron VXB1-1150-20M480 and Skyworks varactor diode, SMV-1249-074LF.
(16) CLKout3 and OSCout also oscillate at start-up at the frequency of the VCXO attached to OSCin port.
(17) Specified by characterization.
(18) Refer to Typical Characteristics for output operation performance at higher frequencies than the minimum maximum output frequency.

6.6 Timing Requirements

See Programming for additional information
MIN NOM MAX UNIT
TECS LE to clock set up time See Figure 1 through Figure 4 25 ns
TDCS Data to clock set up time See Figure 1 25 ns
TCDH Clock to data hold time See Figure 1 8 ns
TCWH Clock pulse width high See Figure 1, Figure 2, and Figure 4 25 ns
TCWL Clock pulse width low See Figure 1, Figure 2, and Figure 4 25 ns
TCES Clock to LE set up time See Figure 1 through Figure 4 25 ns
TEWH LE pulse width See Figure 1, Figure 2, and Figure 4 25 ns
TCR Falling clock to readback time See Figure 4 25 ns
LMK04208 30102303.gif Figure 1. MICROWIRE Input Timing Diagram
LMK04208 30102307.gif Figure 2. MICROWIRE Timing Diagram: Extra CLKuWire Pulses for R0 to R5
LMK04208 30102327.gif Figure 3. MICROWIRE Timing Diagram: Extra CLKuWire Pulses for R0 to R5 with LEuWire Asserted
LMK04208 30102306.gif Figure 4. MICROWIRE Readback Timing Diagram

6.7 Typical Characteristics

LMK04208 30102341.gif
Figure 5. LVDS VOD vs Frequency
LMK04208 30102343.gif
Figure 7. LVPECL with 120-Ω Emitter Resistors
VOD vs Frequency
LMK04208 30102342.gif
Figure 6. LVPECL with 240-Ω Emitter Resistors
VOD vs Frequency