JAJSCH2A September   2016  – June 2017 ADS9120

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset, NAP, and PD
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Converter Module
        1. 7.3.1.1 Sample-and-Hold Circuit
        2. 7.3.1.2 External Reference Source
        3. 7.3.1.3 Internal Oscillator
        4. 7.3.1.4 ADC Transfer Function
      2. 7.3.2 Interface Module
    4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Interleaving Conversion Cycles and Data Transfer Frames
      3. 7.5.3 Data Transfer Protocols
        1. 7.5.3.1 Protocols for Configuring the Device
        2. 7.5.3.2 Protocols for Reading From the Device
          1. 7.5.3.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 7.5.3.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 7.5.3.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.3.2.3.1 Output Clock Source Options with SRC Protocols
            2. 7.5.3.2.3.2 Bus Width Options with SRC Protocols
            3. 7.5.3.2.3.3 Output Data Rate Options with SRC Protocols
      4. 7.5.4 Device Setup
        1. 7.5.4.1 Single Device: All multiSPI™ Options
        2. 7.5.4.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.5.4.3 Multiple Devices: Daisy-Chain Topology
        4. 7.5.4.4 Multiple Devices: Star Topology
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 PD_CNTL Register (address = 010h)
        2. 7.6.1.2 SDI_CNTL Register (address = 014h)
        3. 7.6.1.3 SDO_CNTL Register (address = 018h)
        4. 7.6.1.4 DATA_CNTL Register (address = 01Ch)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Input Driver
      2. 8.1.2 Input Amplifier Selection
      3. 8.1.3 Charge Kickback Filter
      4. 8.1.4 ADC Reference Driver
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power-Supply Recommendations
    1. 9.1 Power-Supply Decoupling
    2. 9.2 Power Saving
      1. 9.2.1 NAP Mode
      2. 9.2.2 PD Mode
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

5 Pin Configuration and Functions

RGE Package
24-Pin VQFN
Top View
ADS9120 PO_bas629.gif

Pin Functions

PIN FUNCTION DESCRIPTION
NAME NO.
AINM 10 Analog input Negative analog input
AINP 9 Analog input Positive analog input
AVDD 13, 14 Power supply Analog power supply for the device
CONVST 1 Digital input Conversion start input pin for the device.
A CONVST rising edge brings the device from ACQ state to CNV state.
CS 24 Digital input Chip-select input pin for the device; active low.
The device takes control of the data bus when CS is low.
The SDO-x pins go to tri-state when CS is high.
DVDD 16 Power supply Interface supply
GND 11, 15 Power supply Ground
NC 3, 6, 12 No connection These pins must be left floating with no external connection
REFM 4, 8 Analog input Reference ground potential
REFP 5, 7 Analog input Reference voltage input
RST 2 Digital input Asynchronous reset input pin for the device.
A low pulse on the RST pin resets the device and all register bits return to a default state.
RVS 21 Digital output Multi-function output pin for the device.
With CS held high, RVS reflects the status of the internal ADCST signal.
With CS low, the status of RVS depends on the output protocol selection.
SCLK 23 Digital input Clock input pin for the serial interface.
All system-synchronous data transfer protocols are timed with respect to the SCLK signal.
SDI 22 Digital input Serial data input pin for the device.
This pin is used to feed the data or command into the device.
SDO-0 20 Digital output Serial communication: data output 0
SDO-1 19 Digital output Serial communication: data output 1
SDO-2 18 Digital output Serial communication: data output 2
SDO-3 17 Digital output Serial communication: data output 3
Thermal pad Supply Exposed thermal pad; connecting this pin to GND is recommended