JAJSCJ4A September   2016  – October 2016 TPS254900-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  FAULT Response
      2. 8.3.2  Cable Compensation
        1. 8.3.2.1 Design Procedure
      3. 8.3.3  D+ and D- Protection
      4. 8.3.4  VBUS OVP Protection
      5. 8.3.5  Output and D+ or D- Discharge
      6. 8.3.6  Port Power Management (PPM)
        1. 8.3.6.1 Benefits of PPM
        2. 8.3.6.2 PPM Details
        3. 8.3.6.3 Implementing PPM in a System With Two Charging Ports (CDP and SDP1)
      7. 8.3.7  Overcurrent Protection
      8. 8.3.8  Undervoltage Lockout
      9. 8.3.9  Thermal Sensing
      10. 8.3.10 Current-Limit Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Truth Table (TT)
      2. 8.4.2 USB BC1.2 Specification Overview
      3. 8.4.3 Standard Downstream Port (SDP) Mode — USB 2.0 and USB 3.0
      4. 8.4.4 Charging Downstream Port (CDP) Mode
      5. 8.4.5 Client Mode
      6. 8.4.6 High-Bandwidth Data-Line Switch
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitance
        2. 9.2.2.2 Output Capacitance
        3. 9.2.2.3 BIAS Capacitance
        4. 9.2.2.4 Output and BIAS TVS
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

5 Pin Configuration and Functions

RVC Package
20-Pin WQFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
BIAS 12 PWR Used for IEC protection. Typically, connect a 2.2-µF capacitor and a transient-voltage suppressor (TVS) to ground and 5.1 kΩ to OUT.
CS 6 O Linear cable compensation current. Connect to divider resistor of front-end dc-dc converter.
CTL1 8 I Logic-level control input for controlling the charging mode and the signal switches; see the Device Truth Table (TT).
CTL2 9 I Logic-level control input for controlling the charging mode and the signal switches; see the Device Truth Table (TT).
DM_IN 14 I/O D– data line to downstream connector
DM_OUT 4 I/O D– data line to upstream USB host controller
DP_IN 13 I/O D+ data line to downstream connector
DP_OUT 5 I/O D+ data line to upstream USB host controller
EN 7 I Logic-level control input for turning the power and signal switches on or off. When EN is low, the device is disabled, and the signal and power switches are OFF.
FAULT 18 O Active-low, open-drain output, asserted during overtemperature, overcurrent, and overvoltage conditions.
GND 11 — Ground connection; should be connected externally to the thermal pad.
ILIM_HI 20 I External resistor used to set the high current-limit threshold.
ILIM_LO 19 I External resistor used to set the low current-limit threshold and the load-detection current threshold.
IMON 1 O This pin sources a scaled-down ratio of current through the internal FET. A resistor from this pin to GND converts current to proportional voltage; used as an analog current monitor.
IN 2,3 PWR Input supply voltage; connect a 0.1-µF or greater ceramic capacitor from IN to GND as close to the IC as possible.
OUT 15,16 PWR Power-switch output
OVP_SEL 10 I Logic-level control input for choosing the OUT overvoltage threshold. When OVP_SEL is low, V(OV_OUT_LOW) is active. When OVP_SEL is high, V(OV_OUT_HIGH) is active.
STATUS 17 O Active-low open-drain output, asserted in load-detect conditions
Thermal pad — — Thermal pad on the bottom of the package
(1) I = Input, O = Output, I/O = Input and output, PWR = Power