JAJSCJ6C September   2016  – October 2024 UCC28950-Q1 , UCC28951-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Dissipation Ratings
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Start-Up Protection Logic
      2. 6.3.2  Voltage Reference (VREF)
      3. 6.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 6.3.4  Soft-Start and Enable (SS/EN)
      5. 6.3.5  Light-Load Power Saving Features
      6. 6.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 6.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 6.3.8  Minimum Pulse (TMIN)
      9. 6.3.9  Burst Mode
      10. 6.3.10 Switching Frequency Setting
      11. 6.3.11 Slope Compensation (RSUM)
      12. 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 6.3.13 Current Sensing (CS)
      14. 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 6.3.15 Synchronization (SYNC)
      16. 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 6.3.17 Supply Voltage (VDD)
      18. 6.3.18 Ground (GND)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Power Loss Budget
        2. 7.2.2.2  Preliminary Transformer Calculations (T1)
        3. 7.2.2.3  QA, QB, QC, QD FET Selection
        4. 7.2.2.4  Selecting LS
        5. 7.2.2.5  Selecting Diodes DB and DC
        6. 7.2.2.6  Output Inductor Selection (LOUT)
        7. 7.2.2.7  Output Capacitance (COUT)
        8. 7.2.2.8  Select FETs QE and QF
        9. 7.2.2.9  Input Capacitance (CIN)
        10. 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 7.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

VDD = 12V, TA = TJ = –40°C to +125°C, CVDD = 1µF, CREF = 1µF, RAB = 22.6kΩ, RCD = 22.6kΩ , REF = 13.3kΩ, RSUM = 124kΩ, RTMIN = 88.7kΩ, RT = 59kΩ connected between RT pin and 5V voltage supply to set FSW = 100kHz (FOSC = 200kHz) (unless otherwise noted). All component designations are from Figure 7-3.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UNDERVOLTAGE LOCKOUT (UVLO)
UVLO_RTH Start threshold 6.75 7.9 V
TA = 25°C 7.3
UVLO_FTH Minimum operating voltage after start 6.15 7.2 V
TA = 25°C 6.7
UVLO_HYST Hysteresis 0.53 0.75 V
TA = 25°C 0.6
SUPPLY CURRENTS
IDD(off) Startup current VDD = 5.2V 270 µA
VDD = 5.2V, TA = 25°C 150
IDD Operating supply current 10 mA
TA = 25°C 5
VREF OUTPUT VOLTAGE
VREF VREF total output range 0 ≤ IR ≤ 20mA, 8V ≤ VDD ≤ 17V 4.925 5.075 V
0 ≤ IR ≤ 20mA, 8V ≤ VDD ≤ 17V, TA = 25°C 5
ISCC Short circuit current VREF = 0V –53 –23 mA
SWITCHING FREQUENCY (½ OF INTERNAL OSCILLATOR FREQUENCY FOSC)
FSW(nom) Total range 92 108 kHz
TA = 25°C 100
DMAX Maximum duty cycle 97%
TA = 25°C 95%
SYNCHRONIZATION
PHSYNC Total range RT = 59kΩ between RT and GND, Input pulses 200kHz, D = 0.5 at SYNC 85 95 °PH
RT = 59kΩ between RT and GND, Input pulses 200kHz, D = 0.5 at SYNC, TA = 25°C 90
FSYNC Total range RT = 59kΩ between RT and 5V; –40 °C ≤ TJ ≤ 125°C 180 220 kHz
TA = 25°C 200
TPW Pulse width 2.2 2.8 µs
TA = 25°C 2.5
ERROR AMPLIFIER
VICM Common-mode input voltage range VICM range ensures parameters, the functionality ensured for 3.6V < VICM < VREF + 0.4V, and –0.4V < VICM < 0.5V 0.5 3.6 V
VIO Offset voltage – 7 7 mV
IBIAS Input bias current –1 1 µA
EAHIGH High-level output voltage V(EA+) – V(EA–) = 500mV, IEAOUT = –0.5mA 3.9 V
V(EA+) – V(EA–) = 500mV, IEAOUT = –0.5mA, TA = 25°C 4.25
EALOW Low-level output voltage V(EA+) – V(EA–) = –500mV, IEAOUT = 0.5mA 0.35 V
V(EA+) – V(EA–) = –500mV, IEAOUT = 0.5mA, TA = 25°C 0.25
ISOURCE Error amplifier source current –8 –0.5 mA
TA = 25°C –3.75
ISINK Error amplifier sink current 2.7 5.75 mA
TA = 25°C 4.6
IVOL Open-loop DC gain TA = 25°C 100 dB
GBW Unity gain bandwidth(1) TA = 25°C 3 MHz
CYCLE-BY-CYCLE CURRENT LIMIT
VCS_LIM CS pin cycle-by-cycle threshold 1.94 2.06 V
TA = 25°C 2
INTERNAL HICCUP MODE SETTINGS
IDS Discharge current to set cycle-by-cycle current limit duration VCS = 2.5V, VVSS = 4V 15 25 µA
VCS = 2.5V, VVSS = 4V, TA = 25°C 20
VHCC Hiccup OFF time threshold 3.2 4.2 V
TA = 25°C 3.6
IHCC Discharge current to set Hiccup Mode OFF Time 1.9 3.2 µA
TA = 25°C 2.55
SOFT START/ENABLE
ISS Charge current VSS = 0V 20 30 µA
TA = 25°C 25
VSS_STD Shutdown, restart threshold 0.25 0.7 V
TA = 25°C 0.5
VSS_PU Pullup threshold 3.3 4.3 V
TA = 25°C 3.7
VSS_CL Clamp voltage 4.2 4.95 V
TA = 25°C 4.65
LIGHT-LOAD EFFICIENCY CIRCUIT
VDCM DCM threshold VDCM = 0.4V, Sweep CS confirm there are OUTE and OUTF pulses, TA = 25°C 0.37 0.39 0.41 V
VDCM = 0.4V, Sweep CS, confirm there are OUTE and OUTF pulses, 0°C ≤ TA ≤ 85°CDCM threshold, (6) 0.364 0.39 0.416 V
VDCM = 0.4V, Sweep CS, confirm there are OUTE and OUTF pulses, –40°C ≤ TA ≤ 125°C(6) 0.35 0.39 0.43 V
IDCM_SRC DCM Sourcing Current CS < DCM threshold 14 26 µA
CS < DCM threshold, TA = 25°C 20
OUTPUTS OUTA, OUTB, OUTC, OUTD, OUTE, OUTF
ISINK/SRC Sink and source peak current(6) TA = 25°C 0.2 A
RSRC Output source resistance IOUT = 20mA 10 35 Ω
IOUT = 20mA, TA = 25°C 20
RSINK Output sink resistance IOUT = 20mA 5 30 Ω
IOUT = 20mA, TA = 25°C 10
THERMAL SHUTDOWN
Rising threshold(6) TA = 25°C 160 °C
Falling threshold(6) TA = 25°C 140 °C
Hysteresis 20 °C
(1) See Figure 6-1 for timing diagram and TABSET1, TABSET2, TCDSET1, TCDSET2 definitions.
(2) See Figure 6-4 for timing diagram and TAFSET1, TAFSET2, TBESET1, TBESET2 definitions.
(3) Pair of outputs OUTC, OUTE and OUTD, OUTF always going high simultaneously.
(4) Outputs A or B are never allowed to go high if both outputs OUTE and OUTF are high.
(5) All delay settings are measured relative to 50% of pulse amplitude.
(6) Verified during characterization only.