JAJSCL6A November   2016  – January 2022 UCC20520

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 PWM Input and Disable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC20520
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
        3. 8.4.2.3 39
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing PWM Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimate Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Dead Time Setting Guidelines
        8. 9.2.2.8 Application Circuits with Output Stage Negative Bias
        9. 9.2.2.9 56
      3. 9.2.3 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
      1. 11.3.1 Certifications
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

6.9 Electrical Characteristics

VVCCI = 3.3 V or VVCCI = 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY CURRENTS
IVCCIVCCI quiescent currentDISABLE = VCCI1.52.0mA
IVDDA,
IVDDB		VDDA and VDDB quiescent currentDISABLE = VCCI1.01.8mA
IVCCIVCCI operating current(f = 500 kHz) current per channel, COUT = 100 pF2.5mA
IVDDA,
IVDDB		VDDA and VDDB operating current(f = 500 kHz) current per channel, COUT = 100 pF2.5mA
VCCI SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS
VVCCI_ONRising threshold VCCI_ON2.552.72.85V
VVCCI_OFFFalling threshold VCCI_OFF2.352.52.65V
VVCCI_HYSThreshold hysteresis0.2V
VDDA/VDDB SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS
VVDDA_ON,
VVDDB_ON		Rising threshold VDDA_ON, VDDB_ON88.59V
VVDDA_OFF,
VVDDB_OFF		Falling threshold VDDA_OFF, VDDB_OFF7.588.5V
VVDDA_HYS,
VVDDB_HYS		Threshold hysteresis0.5V
PWM AND DISABLE
VPWMH, VDISHInput high voltage1.61.82V
VPWML, VDISLInput low voltage0.811.2V
VPWM_HYS, VDIS_HYSInput hysteresis0.8V
VPWMNegative transient, ref to GND, 50 ns pulseNot production tested, bench test only–5V
OUTPUT
IOA+, IOB+Peak output source currentCVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement4A
IOA-, IOB-Peak output sink currentCVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement6A
ROHA, ROHBOutput resistance at high stateIOUT = –10 mA, TA = 25°C, ROHA, ROHBdo not represent drive pull-up performance. See tRISE in Section 6.10 and Section 8.3.4 for details.5Ω
ROLA, ROLBOutput resistance at low stateIOUT = 10 mA, TA = 25°C0.55Ω
VOHA, VOHBOutput voltage at high stateVVDDA, VVDDB = 12 V, IOUT = –10 mA, TA = 25°C11.95V
VOLA, VOLBOutput voltage at low stateVVDDA, VVDDB = 12 V, IOUT = 10 mA, TA = 25°C5.5mV
DEADTIME AND OVERLAP PROGRAMMING
Dead timePull DT pin to VCCI0ns
DT pin is left open, min spec characterized only, tested for outliers815ns
RDT = 20 kΩ160200240ns