JAJSCL6A November   2016  – January 2022 UCC20520

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 PWM Input and Disable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC20520
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
        3. 8.4.2.3 39
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing PWM Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimate Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Dead Time Setting Guidelines
        8. 9.2.2.8 Application Circuits with Output Stage Negative Bias
        9. 9.2.2.9 56
      3. 9.2.3 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
      1. 11.3.1 Certifications
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

6.6 Insulation Specifications

PARAMETERTEST CONDITIONSVALUEUNIT
CLRExternal clearance(1)Shortest terminal to terminal distance through air> 8mm
CPGExternal creepage(1)Shortest terminal to terminal distance across the package surface> 8mm
DTIDistance through insulationDistance through internal isolation (internal clearance)>21µm
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112> 600V
Material groupAccording to IEC 60664-1I
Overvoltage category per IEC 60664-1Rated mains voltage ≤ 600 VRMSI-IV
Rated mains voltage ≤ 1000 VRMSI-III
DIN V VDE 0884-10 (VDE V 0884-10): 2006-2012(2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)2121VPK
VIOWMMaximum isolation working voltageTime dependent dielectric breakdown (TDDB) test, (See Figure 6-1)1500VRMS
2121VDC
VIOTMMaximum transient isolation voltageVTEST = VIOTM
t = 60 sec (qualification)
t = 1 sec (100% production)		8000VPK
VIOSMMaximum surge isolation voltage(3)Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 12800 VPK (qualification)8000VPK
qpdApparent charge(4)Method a, After Input/Output safety test subgroup 2/3. Vini = VIOTM, tini = 60s;

Vpd(m) = 1.2 X VIORM = 2545 VPK, tm = 10s

<5pC
Method a, After environmental tests subgroup 1. Vini = VIOTM, tini = 60s;

Vpd(m) = 1.6 X VIORM = 3394 VPK, tm = 10s

<5

Method b1; At routine test (100% production) and preconditioning (type test)

Vini = VIOTM; tini = 1s;

Vpd(m) = 1.875 * VIORM = 3977 VPK , tm = 1s

<5
CIOBarrier capacitance, input to output(5)VIO = 0.4 sin (2πft), f =1 MHz1.2pF
RIOIsolation resistance, input to outputVIO = 500 V at TA = 25°C> 1012Ω
VIO = 500 V at 100°C ≤ TA ≤ 125°C> 1011
VIO = 500 V at TS =150°C> 109
Pollution degree2
Climatic category40/125/21
UL 1577
VISOWithstand isolation voltageVTEST = VISO = 5700 VRMS, t = 60 sec. (qualification),

VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production)

5700VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.