JAJSCR5C DECEMBER   2016  – October 2017 TLV62569

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode
      2. 7.3.2 100% Duty Cycle Low Dropout Operation
      3. 7.3.3 Soft Startup
      4. 7.3.4 Switch Current Limit
      5. 7.3.5 Under Voltage Lockout
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enabling/Disabling the Device
      2. 7.4.2 Power Good
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Output Filter Design
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Input and Output Capacitor Selection
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
        1. 11.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The following section discusses the design of the external components to complete the power supply design for several input and output voltage options by using typical applications as a reference.

8.2 Typical Application

TLV62569 TLV62569P typ_app_TLV62569P.gif Figure 5. TLV62569 1.8-V Output Application

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 2 as the input parameters.

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage 2.5 V to 5.5 V
Output voltage 1.8 V
Maximum output current 2.0 A

Table 3 lists the components used for the example.

Table 3. List of Components

REFERENCE DESCRIPTION MANUFACTURER(1)
C1 4.7 µF, Ceramic Capacitor, 10 V, X7R, size 0805, GRM21BR71A475KA73L Murata
C2 10 µF, Ceramic Capacitor, 10 V, X7R, size 0805, GRM21BR71A106KE51L Murata
L1 2.2 µH, Power Inductor, size 4mmx4mm, XAL4020-222ME Coilcraft
R1,R2,R3 Chip resistor,1%,size 0603 Std.
C3 Optional, 6.8 pF if it is needed Std.

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TLV62569 device with the WEBENCH® Power Designer.

  1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
  2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
  3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

  • Run electrical simulations to see important waveforms and circuit performance
  • Run thermal simulations to understand board thermal performance
  • Export customized schematic and layout into popular CAD formats
  • Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Setting the Output Voltage

An external resistor divider is used to set output voltage according to Equation 2.

When sizing R2, in order to achieve low current consumption and acceptable noise sensitivity, use a maximum of 200 kΩ for R2. Larger currents through R2 improve noise sensitivity and output voltage accuracy but increase current consumption.

Equation 2. TLV62569 TLV62569P Eq_Vo.gif

A feed forward capacitor, C3 improves the loop bandwidth to make a fast transient response (shown in Figure 19). 6.8-pF capacitance is recommended for R2 of 100-kΩ resistance. A more detailed discussion on the optimization for stability vs. transient response can be found in SLVA289.

8.2.2.3 Output Filter Design

The inductor and output capacitor together provide a low-pass filter. To simplify this process, Table 4 outlines possible inductor and capacitor value combinations. Checked cells represent combinations that are proven for stability by simulation and lab test. Further combinations should be checked for each individual application.

Table 4. Matrix of Output Capacitor and Inductor Combinations

VOUT [V] L [µH](1) COUT [µF](2)
4.7 10 22 2 x 22 100
0.6 ≤ VOUT < 1.2 1 +
2.2 ++(3)
1.2 ≤ VOUT < 1.8 1 + +
2.2 ++(3) +
1.8 ≤ VOUT 1 + + +
2.2 ++(3) + +
(1) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and -30%.
(2) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by +20% and -50%.
(3) This LC combination is the standard value and recommended for most applications.

8.2.2.4 Inductor Selection

The main parameters for inductor selection is inductor value and then saturation current of the inductor. To calculate the maximum inductor current under static load conditions, Equation 3 is given:

Equation 3. TLV62569 TLV62569P Eq_IL_peak_PWM_lvsae8.gif

where

  • IOUT,MAX is the maximum output current
  • ΔIL is the inductor current ripple
  • fSW is the switching frequency
  • L is the inductor value

It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than IL,MAX. In addition, DC resistance and size should also be taken into account when selecting an appropriate inductor.

8.2.2.5 Input and Output Capacitor Selection

The architecture of the TLV62569 allows use of tiny ceramic-type output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are thus recommended. To keep its resistance up to high frequencies and to achieve narrow capacitance variation with temperature, it is recommended to use X7R or X5R dielectric.

The input capacitor is the low impedance energy source for the converter that helps provide stable operation. A low ESR multilayer ceramic capacitor is recommended for best filtering. For most applications, 4.7-μF input capacitance is sufficient; a larger value reduces input voltage ripple.

The TLV62569 is designed to operate with an output capacitor of 10 µF to 47 µF, as outlined in Table 4.

8.2.3 Application Performance Curves

VIN = 5 V, VOUT = 1.8 V, L = 2.2 μH, TA = 25 °C, unless otherwise noted.

TLV62569 TLV62569P D004_SLVSDG1_TLV62569.gif
Figure 6. 1.2-V Output Efficiency
TLV62569 TLV62569P D006_SLVSDG1_TLV62569.gif
Figure 8. 2.5-V Output Efficiency
TLV62569 TLV62569P D005_SLVSDG1_TLV62569.gif
Figure 7. 1.8-V Output Efficiency
TLV62569 TLV62569P D007_SLVSDG1_TLV62569.gif
Figure 9. 3.3-V Output Efficiency
TLV62569 TLV62569P D009_SLVSDG1_TLV62569.gif
VIN = 5 V
Figure 10. Load Regulation
TLV62569 TLV62569P D011_SLVSDG1_TLV62569.gif
VIN = 5 V
Figure 12. Switching Frequency vs Load
TLV62569 TLV62569P D013_SLVSDG1_TLV62569.gif
IOUT = 1 A
Figure 14. PWM Operation
TLV62569 TLV62569P D015_SLVSDG1_TLV62569.gif
IOUT = 2 A
Figure 16. Startup and Shutdown with Load
TLV62569 TLV62569P D017_SLVSDG1_TLV62569.gif
Load Step 0.8 A to 2 A, 1A/μs slew rate
Figure 18. Load Transient
TLV62569 TLV62569P D010_SLVSDG1_TLV62569.gif
VOUT = 1.8 V
Figure 11. Line Regulation
TLV62569 TLV62569P D012_SLVSDG1_TLV62569.gif
IOUT = 1 A
Figure 13. Switching Frequency vs Input Voltage
TLV62569 TLV62569P D014_SLVSDG1_TLV62569.gif
IOUT = 0.1 A
Figure 15. Power Save Mode Operation
TLV62569 TLV62569P D016_SLVSDG1_TLV62569.gif
IOUT = 0.1 A
Figure 17. Startup and Shutdown with Load
TLV62569 TLV62569P D018_SLVSDG1_TLV62569.gif
Load Step 0.8 A to 2 A, 1A/μs slew rate C3 = 6.8 pF
Figure 19. Load Transient