JAJSCS2B July 2016 – June 2018 SN65DSI85-Q1
PRODUCTION DATA.
Address 0x0A is shown in Figure 20 and described in Table 9.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PLL_EN_STAT | Reserved | LVDS_CLK_RANGE | HS_CLK_SRC | ||||
| R-0 | R/W-101 | R/W-0 | |||||
| LEGEND: R/W = Read/Write; R = Read only; W = Write only (reads return undetermined values); R/W1C = Read and Write 1 to Clear |
| BIT | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7 | PLL_EN_STAT | R | 0 | Note: After PLL_EN_STAT = 1, wait at least 3 ms for PLL to lock.
0: PLL not enabled (default) 1: PLL enabled |
| 6–4 | Reserved | Reserved | ||
| 3-1 | LVDS_CLK_RANGE | R/W | 101 | This field selects the frequency range of the LVDS output clock.
000: 25 MHz ≤ LVDS_CLK < 37.5 MHz 001: 37.5 MHz ≤ LVDS_CLK < 62.5 MHz 010: 62.5 MHz ≤ LVDS_CLK < 87.5 MHz 011: 87.5 MHz ≤ LVDS_CLK < 112.5 MHz 100: 112.5 MHz ≤ LVDS_CLK < 137.5 MHz 101: 137.5 MHz ≤ LVDS_CLK ≤ 154 MHz (default) 110: Reserved 111: Reserved |
| 0 | HS_CLK_SRC | R/W | 0 |
0: LVDS pixel clock derived from input REFCLK (default) 1: LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock |