LMG5200 80V、10A GaNハーフ・ブリッジ電力ステージ
- JAJSCT8D March 2015 – March 2017 LMG5200
  
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LMG5200 80V、10A GaNハーフ・ブリッジ電力ステージ

このリソースの元の言語は英語です。翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

1 特長

15mΩ GaN FETおよびドライバを内蔵
電圧定格: 連続80V、パルス100V
PCBレイアウトが簡単になるようパッケージを最適化、アンダーフィル、クリーページ、クリアランスの要件を撤廃
共通ソース・インダクタンスが非常に低いため、ハード・スイッチングのトポロジで過剰なリンギングなしに高いスルー・レートのスイッチングを保証
絶縁および非絶縁アプリケーションに最適
ゲート・ドライバは最高10MHzのスイッチングが可能
内部的なブートストラップ電源電圧クランピングにより、GaN FETオーバードライブを防止
電源レールの低電圧誤動作防止保護
非常に優れた伝搬遅延(標準値29.5ns)およびマッチング(標準値2ns)
低消費電力

2 アプリケーション

広いV_INのマルチMHz同期整流降圧コンバータ
オーディオ用Class-Dアンプ
テレコム、産業、エンタープライズ・コンピューティング用の、48Vのポイント・オブ・ロード(POL)コンバータ
電力密度の高い単相および三相モータ・ドライブ

3 概要

LMG5200デバイスは80V、10AのドライバにGaNハーフ・ブリッジ電力ステージを加えたもので、エンハンスメント・モードの窒化ガリウム(GaN) FETを使用する統合電力ステージ・ソリューションに使用できます。このデバイスは2つの80V GaN FETで構成され、1つの高周波数GaN FETドライバによりハーフ・ブリッジ構成で駆動されます。

GaN FETは逆方向回復時間がほぼゼロで、入力容量C_ISSが非常に小さいため、電力変換において大きな利点があります。すべてのデバイスはボンド・ワイヤを一切使用しないパッケージ・プラットフォームに取り付けられ、パッケージの寄生要素は最小限に抑えられます。LMG5200デバイスは、6mm×8mm×2mmの鉛フリー・パッケージで供給され、簡単にPCBへ取り付けできます。

TTLロジック互換の入力は、VCC電圧にかかわらず最高12Vの入力電圧に耐えられます。独自のブートストラップ電圧クランピング技法により、エンハンスメント・モードGaN FETのゲート電圧が安全な動作範囲内であることが保証されます。

このデバイスは、ディスクリートGaN FETに対して、より使いやすいインターフェイスを提供し、その利点を拡大します。小さなフォーム・ファクタで高周波数、高効率の動作が必要なアプリケーションに理想的なソリューションです。LMG5200をTPS53632Gコントローラとともに使用すると、48Vからポイント・オブ・ロード電圧(0.5～1.5V)への直接変換が可能です。

製品情報⁽¹⁾

型番	パッケージ	本体サイズ(公称)
LMG5200	QFM (9)	6.00mm×8.00mm

利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。

ブロック概略図

4 改訂履歴

Changes from C Revision (December 2016) to D Revision

全般的な編集およびSDSの更新Go
Changed Thermal Information tableGo

Changes from B Revision (January 2016) to C Revision

Changed GaNテクノロジのプレビューから量産データへGo
Added Device Functional Modes Section Go
Added Typical Application Section Go
Updated Power Supply Recommendations Section Go
Added 開発サポート・セクションへのリンクGo

Changes from A Revision (March 2015) to B Revision

Changed part number typographical error in Figure 14Go

Changes from * Revision (March 2015) to A Revision

ブロック概略図の誤字を修正Go
Corrected typographical error in Figure 5Go
Corrected typographical error in Figure 10Go
Corrected typographical error in Figure 11Go

5 Pin Configuration and Functions

MOF Package

9-Pin QFM

Top View

Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NAME	NO.	I/O⁽¹⁾	DESCRIPTION
AGND	7	G	Analog ground. Ground of driver device.
HB	2	P	High-side gate driver bootstrap rail.
HI	4	I	High-side gate driver control input
HS	3	P	High-side GaN FET source connection
LI	5	I	Low-side driver control input
PGND	9	G	Power ground. Low-side GaN FET source. Electrically shorted to AGND pin.
SW	8	P	Switching node. Electrically shorted to HS pin. Ensure low capacitance at this node on PCB.
VCC	6	P	5-V positive gate drive supply
VIN	1	P	Input voltage pin. Electrically connected to high-side GaN FET drain.

(1) I = Input, O = Output, G = Ground, P = Power

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER	MIN	MAX	UNIT
VIN to PGND	0	80	V
VIN to PGND (pulsed, 100-ms maximum duration)⁽²⁾		100	V
HB to AGND	–0.3	86	V
HS to AGND	–5	80	V
HI to AGND	–0.3	12	V
LI to AGND	–0.3	12	V
VCC to AGND	–0.3	6	V
HB to HS	–0.3	6	V
HB to VCC	0	80	V
SW to PGND	–5	80	V
IOUT from SW pin		10	A
Junction temperature, T_J	–40	125	°C
Storage temperature, T_stg	–40	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Device can withstand 1000 pulses up to 100 V of 100-ms duration and less than 1% duty cycle over its lifetime.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	NOM	MAX	UNIT
VCC	4.75	5	5.25	V
LI or HI Input	0		12	V
VIN	0		80	V
HS, SW	–5		80	V
HB	V_HS + 4		V_HS + 5.25	V
HS, SW slew rate⁽¹⁾			50	V/ns
Junction temperature, T_J	–40		125	°C

(1) This parameter is ensured by design. Not tested in production.

6.4 Thermal Information

THERMAL METRIC ⁽¹⁾ ⁽²⁾		LMG5200	UNIT
		MOF (QFM)
		9 PINS
R _θJA	Junction-to-ambient thermal resistance	35	°C/W
R _θJC(top)	Junction-to-case (top) thermal resistance	18	°C/W
R _θJB	Junction-to-board thermal resistance	16	°C/W
ψ _JT	Junction-to-top characterization parameter	1.8	°C/W
ψ _JB	Junction-to-board characterization parameter	16	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator .

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENTS
I_CC	VCC quiescent current	LI = HI = 0 V, VCC = 5 V, HB-HS = 4.6 V		0.08	0.125	mA
I_CCO	Total VCC operating current	f = 500 kHz		3	5	mA
I_HB	HB quiescent current	LI = HI = 0 V, VCC = 5 V, HB-HS = 4.6 V		0.09	0.15	mA
I_HBO	HB operating current	f = 500 kHz, 50% Duty cycle, V_DD = 5 V		1.5	2.5	mA
INPUT PINS
V_IH	High-level input voltage threshold	Rising edge	1.87	2.06	2.22	V
V_IL	Low-level input voltage threshold	Falling edge	1.48	1.66	1.76	V
V_HYS	Hysteresis between rising and falling threshold			400		mV
R_I	Input pulldown resistance		100	200	300	kΩ
UNDERVOLTAGE PROTECTION
V_CCR	V_CC Rising edge threshold	Rising	3.2	3.8	4.5	V
V_CC(hyst)	V_CC UVLO threshold hysteresis			200		mV
V_HBR	HB Rising edge threshold	Rising	2.5	3.2	3.9	V
V_HB(hyst)	HB UVLO threshold hysteresis			200		mV
BOOTSTRAP DIODE
V_DL	Low-current forward voltage	I_VDD-HB = 100 µA		0.45	0.65	V
V_DH	High current forward voltage	I_VDD-HB = 100 mA		0.9	1.0	V
R_D	Dynamic resistance	I_VDD-HB = 100 mA		1.85	2.8	Ω
	HB-HS clamp	Regulation Voltage	4.65	5	5.2	V
t_BS	Bootstrap diode reverse recovery time	I_F = 100 mA, IR = 100 mA		40		ns
Q_RR	Bootstrap diode reverse recovery charge	V_VIN = 50 V		2		nC
POWER STAGE
R_DS(ON)HS	High-side GaN FET on-resistance	LI = 0 V, HI = VCC=5 V, HB-HS = 5 V, VIN-SW = 10 A, T_J = 25℃		15	20	mΩ
R_DS(ON)LS	Low-side GaN FET on-resistance	LI = VCC = 5V, HI = 0 V, HB-HS = 5 V, SW-PGND = 10 A, T_J = 25℃		15	20	mΩ
V_SD	GaN 3rd quadrant conduction drop	I_SD = 500 mA, V_IN floating, V_VCC = 5 V, HI = LI = 0 V		2		V
I_L-VIN-SW	Leakage from VIN to SW when the high-side GaN FET and low-side GaN FET are off	VIN = 80 V, HI = LI = 0 V, V_VCC = 5 V, T_J= 25℃		25	150	µA
I_L-SW-GND	Leakage from SW to GND when the high-side GaN FET and low-side GaN FET are off	SW = 80 V, HI = LI = 0 V, V_VCC = 5V, T_J = 25℃		25	150	µA
C_OSS	Output capacitance of high-side GaN FET and low-side GaN FET	V_DS=40 V, V_GS= 0V (HI = LI = 0 V)		266		pF
Q_G	Total gate charge	V_DS=40 V, I_D= 10A, V_GS= 5 V		3.8		nC
Q_OSS	Output charge	V_DS=40 V, I_D= 10 A		21		nC
Q_RR	Source-to-drain reverse recovery charge	Not including internal driver bootstrap diode		0		nC
t_HIPLH	Propagation delay: HI rising⁽²⁾	LI = 0 V, VCC = 5 V, HB-HS = 5 V, VIN = 30 V		29.5	50	ns
t_HIPHL	Propagation delay: HI falling⁽²⁾	LI = 0 V, VCC = 5 V, HB-HS = 5 V, VIN = 30 V		29.5	50	ns
t_LPLH	Propagation delay: LI rising⁽²⁾	HI = 0 V, VCC = 5 V, HB-HS = 5 V, VIN = 30 V		29.5	50	ns
t_LPHL	Propagation delay: LI falling⁽²⁾	HI = 0 V, VCC = 5 V, HB-HS = 5 V, VIN = 30 V		29.5	50	ns
t_MON	Delay matching: LI high and HI low⁽²⁾			2	8	ns
t_MOFF	Delay matching: LI low and HI high⁽²⁾			2	8	ns
t_PW	Minimum input pulse width that changes the output			10		ns

(1) Parameters that show only a typical value are ensured by design and may not be tested in production.

(2) See Propagation Delay and Mismatch Measurement.

6.6 Typical Characteristics

All the curves are based on measurements made on a PCB design with dimensions of 3.2 inches (W) × 2.7 inches (L) × 0.062 inch (T) and 4 layers of 2 oz copper.

The safe operating area (SOA) curves displays the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. A buck converter is used for measuring the SOA. Figure 2 outlines the temperature and airflow conditions required for a given load current. The area under the curve dictates the SOA for different airflow conditions.

V_DD = 5 V

Figure 1. V_DD Supply Current vs Switching Frequency

GaN third quadrant conduction.

Figure 3. Source-to-Drain Current vs Source-to-Drain Voltage

V_IN = 48 V

V_OUT = 5 V

f_SW = 1 MHz

Figure 2. Safe Operating Area

Figure 4. GaN FET On-Resistance vs Junction Temperature

7 Parameter Measurement Information

7.1 Propagation Delay and Mismatch Measurement

Figure 5 shows the typical test setup used to measure the propagation mismatch. As the gate drives are not accessible, pullup and pulldown resistors in this test circuit are used to indicate when the low-side GaN FET turns ON and the high-side GaN FET turns OFF and vice versa to measure the t_MON and t_MOFF parameters. Resistance values used in this circuit for the pullup and pulldown resistors are in the order of 1 kΩ; the current sources used are 2 A.

Figure 6 through Figure 9 show propagation delay measurement waveforms. For turnon propagation delay measurements, the current sources are not used. For turnoff time measurements, the current sources are set to 2 A, and a voltage clamp limit is also set, referred to as VIN_(CLAMP). When measuring the high-side component turnoff delay, the current source across the high-side FET is turned on, the current source across the low-side FET is off, HI transitions from high-to-low, and output voltage transitions from V_IN to V_IN(CLAMP). Similarly, for low-side component turnoff propagation delay measurements, the high-side component current source is turned off, and the low-side component current source is turned on, LI transitions from high to low and the output transitions from GND potential to V_IN(CLAMP). The time between the transition of LI and the output change is the propagation delay time.