JAJSCV7E august   2016  – november 2020 DS90UB933-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing For PCLK
    7. 6.7  AC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 6.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    9. 6.9  Serializer Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Line Rate Calculations for the DS90UB933/934
      3. 7.3.3 Error Detection
      4. 7.3.4 Synchronizing Multiple Cameras
      5. 7.3.5 General Purpose I/O (GPIO) Descriptions
      6. 7.3.6 LVCMOS V(VDDIO) Option
      7. 7.3.7 Pixel Clock Edge Select (TRFB / RRFB)
      8. 7.3.8 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DS90UB933/934 Operation With External Oscillator as Reference Clock
      2. 7.4.2 DS90UB933/934 Operation With Pixel Clock From Imager as Reference Clock
      3. 7.4.3 MODE Pin on Serializer
      4. 7.4.4 Internal Oscillator
      5. 7.4.5 Built-In Self Test
      6. 7.4.6 BIST Configuration and Status
      7. 7.4.7 Sample BIST Sequence
    5. 7.5 Programming
      1. 7.5.1 Programmable Controller
      2. 7.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 7.5.3 I2C Pass-Through
      4. 7.5.4 Slave Clock Stretching
      5. 7.5.5 IDX Address Decoder on the Serializer
      6. 7.5.6 Multiple Device Addressing
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
      2. 8.1.2 Power-Up Requirements and PDB Pin
      3. 8.1.3 AC Coupling
      4. 8.1.4 Transmission Media
    2. 8.2 Typical Applications
      1. 8.2.1 Coax Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 STP Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 62
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Interconnect Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集

6.6 Recommended Serializer Timing For PCLK

Over recommended operating supply and temperature ranges unless otherwise specified.(1) (2)
PARAMETERTEST CONDITIONSPIN / FREQMINNOMMAXUNIT
tTCPTransmit clock period10-bit mode
50 MHz – 100 MHz		7.52T20ns
12-bit mode
37.5 MHz - 100 MHz		10T26.67ns
tTCIHTransmit clock
input high time		0.4T0.5T0.6T
tTCILTransmit clock
input low time		0.4T0.5T0.6T
tCLKTPCLK input transition time (Figure 6-7)10-bit mode
50 MHz – 100 MHz		0.05T0.25T0.3T
12-bit mode
37.5 MHz – 100 MHz		0.05T0.25T0.3T
tJIT0PCLK input jitter (3)
(PCLK from imager mode)		LPF = ƒ/20, CDR PLL Loop BW = ƒ/15, BER = 1E-10ƒPCLK = 37.5 – 100 MHz(5)0.45UI
tJIT1PCLK input jitter(3)
(External oscillator mode)		LPF = ƒ/20, CDR PLL Loop BW = ƒ/15, BER = 1E-10ƒPCLK = 37.5 – 100 MHz(5)1T
tJIT2External oscillator jitter(3)(4)LPF = ƒ/20, CDR PLL Loop BW = ƒ/15, BER = 1E-10, paired with DS90UB934-Q1 deserializerƒOSC = 25 – 66.67 MHz(6)0.45UI
ΔOSCExternal Oscillator Frequency StabilityƒOSC = 25 – 66.67 MHz(6)±50ppm
tDCCLKOUT duty cycle (external oscillator mode)ƒOSC = 25 – 66.67 MHz(6)45%50%55%
(1) Recommended input timing requirements are input specifications and not tested in production.
(2) T is the period of the PCLK.
(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at Section 6.3 at the time of product characterization and are not verified.
(4) 0.45UI maximum when used with DS90UB934-Q1 deserializer. When used with DS90UB914A-Q1 deserializer, the maximum is 0.3UI.
(5) ƒPCLK denotes input PCLK frequency to the device.
(6) ƒOSC denotes input external oscillator frequency to the device (GPO3/CLKIN).