JAJSCW4C december   2016  – september 2020 CC2640R2F

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram – RGZ Package
    2. 7.2 Signal Descriptions – RGZ Package
    3. 7.3 Pin Diagram – RHB Package
    4. 7.4 Signal Descriptions – RHB Package
    5. 7.5 Pin Diagram – YFV (Chip Scale, DSBGA) Package
    6. 7.6 Signal Descriptions – YFV (Chip Scale, DSBGA) Package
    7. 7.7 Pin Diagram – RSM Package
    8. 7.8 Signal Descriptions – RSM Package
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Power Consumption Summary
    5. 8.5  General Characteristics
    6. 8.6  125-kbps Coded (Bluetooth 5) – RX
    7. 8.7  125-kbps Coded (Bluetooth 5) – TX
    8. 8.8  500-kbps Coded (Bluetooth 5) – RX
    9. 8.9  500-kbps Coded (Bluetooth 5) – TX
    10. 8.10 1-Mbps GFSK (Bluetooth low energy) – RX
    11. 8.11 1-Mbps GFSK (Bluetooth low energy) – TX
    12. 8.12 2-Mbps GFSK (Bluetooth 5) – RX
    13. 8.13 2-Mbps GFSK (Bluetooth 5) – TX
    14. 8.14 24-MHz Crystal Oscillator (XOSC_HF)
    15. 8.15 32.768-kHz Crystal Oscillator (XOSC_LF)
    16. 8.16 48-MHz RC Oscillator (RCOSC_HF)
    17. 8.17 32-kHz RC Oscillator (RCOSC_LF)
    18. 8.18 ADC Characteristics
    19. 8.19 Temperature Sensor
    20. 8.20 Battery Monitor
    21. 8.21 Continuous Time Comparator
    22. 8.22 Low-Power Clocked Comparator
    23. 8.23 Programmable Current Source
    24. 8.24 Synchronous Serial Interface (SSI)
    25. 8.25 DC Characteristics
    26. 8.26 Thermal Resistance Characteristics
    27. 8.27 Timing Requirements
    28. 8.28 Switching Characteristics
    29. 8.29 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Functional Block Diagram
    3. 9.3  Main CPU
    4. 9.4  RF Core
    5. 9.5  Sensor Controller
    6. 9.6  Memory
    7. 9.7  Debug
    8. 9.8  Power Management
    9. 9.9  Clock Systems
    10. 9.10 General Peripherals and Modules
    11. 9.11 Voltage Supply Domains
    12. 9.12 System Architecture
  10. 10Application, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 5 × 5 External Differential (5XD) Application Circuit
      1. 10.2.1 Layout
    3. 10.3 4 × 4 External Single-ended (4XS) Application Circuit
      1. 10.3.1 Layout
  11. 11Device and Documentation Support
    1. 11.1  Device Nomenclature
    2. 11.2  Tools and Software
    3. 11.3  Documentation Support
    4. 11.4  Texas Instruments Low-Power RF Website
    5. 11.5  Low-Power RF eNewsletter
    6. 11.6  サポート・リソース
    7. 11.7  Trademarks
    8. 11.8  静電気放電に関する注意事項
    9. 11.9  Export Control Notice
    10. 11.10 用語集
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

8.18 ADC Characteristics

Tc = 25°C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Input voltage range0VDDSV
Resolution12Bits
Sample rate200ksps
OffsetInternal 4.3-V equivalent reference(2)2LSB
Gain errorInternal 4.3-V equivalent reference(2)2.4LSB
DNL(3)Differential nonlinearity>–1LSB
INL(4)Integral nonlinearity±3LSB
ENOBEffective number of bitsInternal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone		9.8Bits
VDDS as reference, 200 ksps, 9.6-kHz input tone10
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone		11.1
THDTotal harmonic distortionInternal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone		–65dB
VDDS as reference, 200 ksps, 9.6-kHz input tone–69
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone		–71
SINAD,
SNDR		Signal-to-noise
and
Distortion ratio		Internal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone		60dB
VDDS as reference, 200 ksps, 9.6-kHz input tone63
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone		69
SFDRSpurious-free dynamic rangeInternal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone		67dB
VDDS as reference, 200 ksps, 9.6-kHz input tone68
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone		73
Conversion timeSerial conversion, time-to-output, 24-MHz clock50clock-cycles
Current consumptionInternal 4.3-V equivalent reference(2)0.66mA
Current consumptionVDDS as reference0.75mA
Reference voltageEquivalent fixed internal reference (input voltage scaling enabled). For best accuracy, the ADC conversion should be initiated through the TIRTOS API in order to include the gain/offset compensation factors stored in FCFG1.4.3(2)(5)V
Reference voltageFixed internal reference (input voltage scaling disabled). For best accuracy, the ADC conversion should be initiated through the TIRTOS API in order to include the gain/offset compensation factors stored in FCFG1. This value is derived from the scaled value (4.3 V) as follows:
Vref = 4.3 V × 1408 / 4095		1.48V
Reference voltageVDDS as reference (Also known as RELATIVE) (input voltage scaling enabled)VDDSV
Reference voltageVDDS as reference (Also known as RELATIVE) (input voltage scaling disabled)VDDS / 2.82(5)V
Input impedance200 ksps, voltage scaling enabled. Capacitive input, Input impedance depends on sampling frequency and sampling time>1MΩ
(1) Using IEEE Std 1241™-2010 for terminology and test methods.
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V.
(3) No missing codes. Positive DNL typically varies from +0.3 to +3.5, depending on device (see Figure 8-21).
(4) For a typical example, see Figure 8-22.
(5) Applied voltage must be within absolute maximum ratings (Section 8.1) at all times.