JAJSCX6B January   2017  – July 2019 LMK04610

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions: LMK04610
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Digital Input and Output Characteristics (CLKin_SEL, STATUSx, SYNC, RESETN)
    6. 8.6  Clock Input Characteristics (CLKinX)
    7. 8.7  Clock Input Characteristics (OSCin)
    8. 8.8  PLL1 Specification Characteristics
    9. 8.9  PLL2 Specification Characteristics
    10. 8.10 Clock Output Type Characteristics (CLKoutX)
    11. 8.11 Oscillator Output Characteristics (OSCout)
    12. 8.12 Jitter and Phase Noise Characteristics for CLKoutX and OSCout
    13. 8.13 Clock Output Skew and Isolation Characteristics
    14. 8.14 Clock Output Delay Characteristics
    15. 8.15 DEFAULT POWER on RESET CLOCK OUTPUT Characteristics
    16. 8.16 Power Supply Characteristics
    17. 8.17 Typical Power Supply Noise Rejection Characteristics
    18. 8.18 SPI Interface Timing
    19. 8.19 Timing Diagram
    20. 8.20 Typical Characteristics
      1. 8.20.1 Clock Output AC Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Differential Voltage Measurement Terminology
    2. 9.2 Output Termination Scheme
      1. 9.2.1 HSDS 4/6/8mA
      2. 9.2.2 HCSL
      3. 9.2.3 LVCMOS
  10. 10Detailed Description
    1. 10.1 Overview
      1. 10.1.1 Jitter Cleaning
      2. 10.1.2 Two Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
      3. 10.1.3 VCXO Buffered Output
      4. 10.1.4 Frequency Holdover
      5. 10.1.5 Integrated Programmable PLL1 and PLL2 Loop Filter
      6. 10.1.6 Internal VCOs
      7. 10.1.7 Clock Distribution
        1. 10.1.7.1 Output Clock Divider
        2. 10.1.7.2 Output Clock Delay
        3. 10.1.7.3 Glitchless Half-Step and Glitchless Analog Delay
        4. 10.1.7.4 Programmable Output Formats
        5. 10.1.7.5 Clock Output SYNChronization
      8. 10.1.8 Status Pins
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
        1. 10.3.1.1 Input Clock Switching
          1. 10.3.1.1.1 Input Clock Switching – Register Select Mode
          2. 10.3.1.1.2 Input Clock Switching – Pin Select Mode (CLKin_SEL)
          3. 10.3.1.1.3 Input Clock Switching – Automatic Mode
        2. 10.3.1.2 Loss of Signal Detection – LOS
          1. 10.3.1.2.1 LOS – Assertion
          2. 10.3.1.2.2 LOS – Reference Clock Recovery
        3. 10.3.1.3 Driving CLKin and OSCin Inputs
          1. 10.3.1.3.1 Driving CLKin and OSCin Pins With a Differential Source
          2. 10.3.1.3.2 Driving CLKin and OSCin Pins With a Single-Ended Source
      2. 10.3.2 Clock Outputs (CLKoutX)
        1. 10.3.2.1 HCSL
        2. 10.3.2.2 HSDS
        3. 10.3.2.3 SYNC
        4. 10.3.2.4 Digital Delay
          1. 10.3.2.4.1 Fixed Digital Delay
          2. 10.3.2.4.2 Dynamic Digital Delay
        5. 10.3.2.5 Analog Delay
      3. 10.3.3 OSCout
        1. 10.3.3.1 Pin-Controlled OSCout Divider
      4. 10.3.4 STATUS0/1 and SYNC Pin Functions
        1. 10.3.4.1 Common STATUS0/1 and SYNC Pin Functions
        2. 10.3.4.2 Additional STATUS0 Pin Functions
        3. 10.3.4.3 Additional SYNC Pin Functions
      5. 10.3.5 PLL1 and PLL2
        1. 10.3.5.1 PLL1
          1. 10.3.5.1.1 PLL1 Proportional Modes
          2. 10.3.5.1.2 PLL1 Higher Order Poles
        2. 10.3.5.2 PLL2
          1. 10.3.5.2.1 PLL2 Divider
          2. 10.3.5.2.2 PLL2 Input Modes
          3. 10.3.5.2.3 PLL2 Loop Filter
          4. 10.3.5.2.4 PLL2 3rd Order Loop Filter
          5. 10.3.5.2.5 PLL2 Voltage Controlled Oscillator (VCO)
          6. 10.3.5.2.6 Examples of PLL2 Setting
        3. 10.3.5.3 Digital Lock Detect
          1. 10.3.5.3.1 Calculating Digital Lock Detect Frequency Accuracy
      6. 10.3.6 Holdover
        1. 10.3.6.1 Holdover Flowchart
        2. 10.3.6.2 Enable Holdover
          1. 10.3.6.2.1 Automatic Tracked CTRL_VCXO Holdover Mode
        3. 10.3.6.3 Enter Holdover
          1. 10.3.6.3.1 LOS_x Detect
          2. 10.3.6.3.2 PLL1 DLD Detect
          3. 10.3.6.3.3 CTRL_VCXO Rail Detect
            1. 10.3.6.3.3.1 Absolute Limits
            2. 10.3.6.3.3.2 Relative Limits
          4. 10.3.6.3.4 Manual Holdover Enable – Register Control
          5. 10.3.6.3.5 Manual Holdover Enable – Pin Control
          6. 10.3.6.3.6 Start-Up into Holdover
        4. 10.3.6.4 During Holdover
        5. 10.3.6.5 Exiting Holdover
        6. 10.3.6.6 Holdover Frequency Accuracy
        7. 10.3.6.7 Holdover Mode – Automatic Exit by LOS Deassertion
        8. 10.3.6.8 Holdover Mode – Automatic Exit of Holdover With Holdover Counter
      7. 10.3.7 JEDEC JESD204B
        1. 10.3.7.1 SYNC Pins
        2. 10.3.7.2 SYNC modes
        3. 10.3.7.3 SYSREF Modes
          1. 10.3.7.3.1 SYSREF Pulser
            1. 10.3.7.3.1.1 SPI Pulser Mode
            2. 10.3.7.3.1.2 Pin Pulser Mode
            3. 10.3.7.3.1.3 Multiple SYSREF Frequencies
          2. 10.3.7.3.2 Continuous SYSREF
          3. 10.3.7.3.3 SYSREF Request
        4. 10.3.7.4 How to Enable SYSREF
          1. 10.3.7.4.1 Setup Example 1: Pulser Mode, Pin Controlled
          2. 10.3.7.4.2 Setup Example 2: Pulser Mode, Spi Controlled
      8. 10.3.8 Zero Delay Mode (ZDM)
      9. 10.3.9 Power-Up Sequence
    4. 10.4 Device Functional Modes
      1. 10.4.1 Dual PLL
      2. 10.4.2 Single PLL
      3. 10.4.3 PLL2 Bypass
      4. 10.4.4 Clock Distribution
    5. 10.5 Programming
      1. 10.5.1 Recommended Programming Sequence
        1. 10.5.1.1 Readback
    6. 10.6 Register Maps
      1. 10.6.1 Register Map for Device Programming
      2. 10.6.2 Device Register Descriptions
        1. 10.6.2.1   CONFIGA
        2. 10.6.2.2   RESERVED1
        3. 10.6.2.3   RESERVED2
        4. 10.6.2.4   CHIP_TYPE
        5. 10.6.2.5   CHIP_ID_BY1
        6. 10.6.2.6   CHIP_ID_BY0
        7. 10.6.2.7   CHIP_VER
        8. 10.6.2.8   RESERVED3
        9. 10.6.2.9   RESERVED4
        10. 10.6.2.10  RESERVED5
        11. 10.6.2.11  RESERVED6
        12. 10.6.2.12  RESERVED7
        13. 10.6.2.13  VENDOR_ID_BY1
        14. 10.6.2.14  VENDOR_ID_BY0
        15. 10.6.2.15  RESERVED8
        16. 10.6.2.16  RESERVED9
        17. 10.6.2.17  STARTUP_CFG
        18. 10.6.2.18  STARTUP
        19. 10.6.2.19  DIGCLKCTRL
        20. 10.6.2.20  PLL2REFCLKDIV
        21. 10.6.2.21  GLBL_SYNC_SYSREF
        22. 10.6.2.22  CLKIN_CTRL0
        23. 10.6.2.23  CLKIN_CTRL1
        24. 10.6.2.24  CLKIN0CTRL
        25. 10.6.2.25  CLKIN1CTRL
        26. 10.6.2.26  CLKIN0RDIV_BY1
        27. 10.6.2.27  CLKIN0RDIV_BY0
        28. 10.6.2.28  CLKIN1RDIV_BY1
        29. 10.6.2.29  CLKIN1RDIV_BY0
        30. 10.6.2.30  CLKIN0LOS_REC_CNT
        31. 10.6.2.31  CLKIN0LOS_LAT_SEL
        32. 10.6.2.32  CLKIN1LOS_REC_CNT
        33. 10.6.2.33  CLKIN1LOS_LAT_SEL
        34. 10.6.2.34  CLKIN_SWCTRL0
        35. 10.6.2.35  CLKIN_SWCTRL1
        36. 10.6.2.36  CLKIN_SWCTRL2
        37. 10.6.2.37  OSCIN_CTRL
        38. 10.6.2.38  OSCOUT_CTRL
        39. 10.6.2.39  OSCOUT_DIV
        40. 10.6.2.40  OSCOUT_DRV
        41. 10.6.2.41  OUTCH_SWRST
        42. 10.6.2.42  OUTCH1CNTL0
        43. 10.6.2.43  OUTCH1CNTL1
        44. 10.6.2.44  OUTCH2CNTL0
        45. 10.6.2.45  OUTCH2CNTL1
        46. 10.6.2.46  OUTCH34CNTL0
        47. 10.6.2.47  OUTCH34CNTL1
        48. 10.6.2.48  OUTCH5CNTL0
        49. 10.6.2.49  OUTCH5CNTL1
        50. 10.6.2.50  OUTCH6CNTL0
        51. 10.6.2.51  OUTCH6CNTL1
        52. 10.6.2.52  OUTCH78CNTL0
        53. 10.6.2.53  OUTCH78CNTL1
        54. 10.6.2.54  OUTCH9CNTL0
        55. 10.6.2.55  OUTCH9CNTL1
        56. 10.6.2.56  OUTCH10CNTL0
        57. 10.6.2.57  OUTCH10CNTL1
        58. 10.6.2.58  OUTCH1DIV_BY1
        59. 10.6.2.59  OUTCH1DIV_BY0
        60. 10.6.2.60  OUTCH2DIV_BY1
        61. 10.6.2.61  OUTCH2DIV_BY0
        62. 10.6.2.62  OUTCH34DIV_BY1
        63. 10.6.2.63  OUTCH34DIV_BY0
        64. 10.6.2.64  OUTCH5DIV_BY1
        65. 10.6.2.65  OUTCH5DIV_BY0
        66. 10.6.2.66  OUTCH6DIV_BY1
        67. 10.6.2.67  OUTCH6DIV_BY0
        68. 10.6.2.68  OUTCH78DIV_BY1
        69. 10.6.2.69  OUTCH78DIV_BY0
        70. 10.6.2.70  OUTCH9DIV_BY1
        71. 10.6.2.71  OUTCH9DIV_BY0
        72. 10.6.2.72  OUTCH10DIV_BY1
        73. 10.6.2.73  OUTCH10DIV_BY0
        74. 10.6.2.74  OUTCH_DIV_INV
        75. 10.6.2.75  PLL1CTRL0
        76. 10.6.2.76  PLL1CTRL1
        77. 10.6.2.77  PLL1CTRL2
        78. 10.6.2.78  PLL1_SWRST
        79. 10.6.2.79  PLL1WNDWSIZE
        80. 10.6.2.80  PLL1STRCELL
        81. 10.6.2.81  PLL1CPSETTING
        82. 10.6.2.82  PLL1CPSETTING_FL
        83. 10.6.2.83  PLL1_HOLDOVER_CTRL1
        84. 10.6.2.84  PLL1_HOLDOVER_MAXCNT_BY3
        85. 10.6.2.85  PLL1_HOLDOVER_MAXCNT_BY2
        86. 10.6.2.86  PLL1_HOLDOVER_MAXCNT_BY1
        87. 10.6.2.87  PLL1_HOLDOVER_MAXCNT_BY0
        88. 10.6.2.88  PLL1_NDIV_BY1
        89. 10.6.2.89  PLL1_NDIV_BY0
        90. 10.6.2.90  PLL1_LOCKDET_CYC_CNT_BY2
        91. 10.6.2.91  PLL1_LOCKDET_CYC_CNT_BY1
        92. 10.6.2.92  PLL1_LOCKDET_CYC_CNT_BY0
        93. 10.6.2.93  PLL1_STRG_BY4
        94. 10.6.2.94  PLL1_STRG_BY3
        95. 10.6.2.95  PLL1_STRG_BY2
        96. 10.6.2.96  PLL1_STRG_BY1
        97. 10.6.2.97  PLL1_STRG_BY0
        98. 10.6.2.98  PLL1RCCLKDIV
        99. 10.6.2.99  PLL2_CTRL0
        100. 10.6.2.100 PLL2_CTRL1
        101. 10.6.2.101 PLL2_CTRL2
        102. 10.6.2.102 PLL2_SWRST
        103. 10.6.2.103 PLL2_LF_C4R4
        104. 10.6.2.104 PLL2_LF_C3R3
        105. 10.6.2.105 PLL2_CP_SETTING
        106. 10.6.2.106 PLL2_NDIV_BY1
        107. 10.6.2.107 PLL2_NDIV_BY0
        108. 10.6.2.108 PLL2_RDIV_BY1
        109. 10.6.2.109 PLL2_RDIV_BY0
        110. 10.6.2.110 PLL2_STRG_INIT_BY1
        111. 10.6.2.111 PLL2_STRG_INIT_BY0
        112. 10.6.2.112 RAILDET_UP
        113. 10.6.2.113 RAILDET_LOW
        114. 10.6.2.114 PLL2_AC_CTRL
        115. 10.6.2.115 PLL2_CURR_STOR_CELL
        116. 10.6.2.116 PLL2_AC_THRESHOLD
        117. 10.6.2.117 PLL2_AC_STRT_THRESHOLD
        118. 10.6.2.118 PLL2_AC_WAIT_CTRL
        119. 10.6.2.119 PLL2_AC_JUMPSTEP
        120. 10.6.2.120 PLL2_LD_WNDW_SIZE
        121. 10.6.2.121 PLL2_LD_WNDW_SIZE_INITIAL
        122. 10.6.2.122 PLL2_LOCKDET_CYC_CNT_BY2
        123. 10.6.2.123 PLL2_LOCKDET_CYC_CNT_BY1
        124. 10.6.2.124 PLL2_LOCKDET_CYC_CNT_BY0
        125. 10.6.2.125 PLL2_LOCKDET_CYC_CNT_INITIAL_BY2
        126. 10.6.2.126 PLL2_LOCKDET_CYC_CNT_INITIAL_BY1
        127. 10.6.2.127 PLL2_LOCKDET_CYC_CNT_INITIAL_BY0
        128. 10.6.2.128 IOCTRL_SPI0
        129. 10.6.2.129 IOCTRL_SPI1
        130. 10.6.2.130 IOTEST_SDIO
        131. 10.6.2.131 IOTEST_SCL
        132. 10.6.2.132 IOTEST_SCS
        133. 10.6.2.133 IOCTRL_STAT0
        134. 10.6.2.134 IOCTRL_STAT1
        135. 10.6.2.135 STAT1MUX
        136. 10.6.2.136 STAT0MUX
        137. 10.6.2.137 STATPLL2CLKDIV
        138. 10.6.2.138 IOTEST_STAT0
        139. 10.6.2.139 IOTEST_STAT1
        140. 10.6.2.140 IOCTRL_SYNC
        141. 10.6.2.141 DUMMY_REGISTER_1
        142. 10.6.2.142 IOCTRL_CLKINSEL1
        143. 10.6.2.143 IOTEST_CLKINSEL1
        144. 10.6.2.144 PLL1_TSTMODE
        145. 10.6.2.145 PLL2_CTRL
        146. 10.6.2.146 STATUS
        147. 10.6.2.147 PLL2_DLD_EN
        148. 10.6.2.148 PLL2_DUAL_LOOP
        149. 10.6.2.149 RESERVED10
        150. 10.6.2.150 CH1_DDLY_BY0
        151. 10.6.2.151 CH2_DDLY_BY0
        152. 10.6.2.152 CH34_DDLY_BY0
        153. 10.6.2.153 CH5_DDLY_BY0
        154. 10.6.2.154 CH6_DDLY_BY0
        155. 10.6.2.155 CH78_DDLY_BY0
        156. 10.6.2.156 CH9_DDLY_BY0
        157. 10.6.2.157 CH10_DDLY_BY0
        158. 10.6.2.158 OUTCH1_JESD_CTRL
        159. 10.6.2.159 OUTCH2_JESD_CTRL
        160. 10.6.2.160 OUTCH3_JESD_CTRL
        161. 10.6.2.161 OUTCH4_JESD_CTRL
        162. 10.6.2.162 OUTCH5_JESD_CTRL
        163. 10.6.2.163 OUTCH6_JESD_CTRL
        164. 10.6.2.164 OUTCH7_JESD_CTRL
        165. 10.6.2.165 OUTCH8_JESD_CTRL
        166. 10.6.2.166 OUTCH9_JESD_CTRL
        167. 10.6.2.167 OUTCH10_JESD_CTRL
        168. 10.6.2.168 CLKMUXVECTOR
        169. 10.6.2.169 OUTCH1CNTL2
        170. 10.6.2.170 OUTCH2CNTL2
        171. 10.6.2.171 OUTCH34CNTL2
        172. 10.6.2.172 OUTCH5CNTL2
        173. 10.6.2.173 OUTCH6CNTL2
        174. 10.6.2.174 OUTCH78CNTL2
        175. 10.6.2.175 OUTCH9CNTL2
        176. 10.6.2.176 OUTCH10CNTL2
        177. 10.6.2.177 OUTCH1_JESD_CTRL1
        178. 10.6.2.178 OUTCH2_JESD_CTRL1
        179. 10.6.2.179 OUTCH3_JESD_CTRL1
        180. 10.6.2.180 OUTCH4_JESD_CTRL1
        181. 10.6.2.181 OUTCH5_JESD_CTRL1
        182. 10.6.2.182 OUTCH6_JESD_CTRL1
        183. 10.6.2.183 OUTCH7_JESD_CTRL1
        184. 10.6.2.184 OUTCH8_JESD_CTRL1
        185. 10.6.2.185 OUTCH9_JESD_CTRL1
        186. 10.6.2.186 OUTCH10_JESD_CTRL1
        187. 10.6.2.187 SYSREF_PLS_CNT
        188. 10.6.2.188 SYNCMUX
        189. 10.6.2.189 IOTEST_SYNC
        190. 10.6.2.190 OUTCH_ZDM
        191. 10.6.2.191 PLL2_CTRL3
        192. 10.6.2.192 PLL1_HOLDOVER_CTRL0
        193. 10.6.2.193 IOCTRL_SYNC_1
        194. 10.6.2.194 OUTCH_TOP_JESD_CTRL
        195. 10.6.2.195 OUTCH_BOT_JESD_CTRL
        196. 10.6.2.196 OUTCH_JESD_CTRL1
        197. 10.6.2.197 PLL2_CTRL4
        198. 10.6.2.198 PLL2_CTRL5
        199. 10.6.2.199 PLL2_CTRL6
        200. 10.6.2.200 PLL2_CTRL7
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Digital Lock Detect Frequency Accuracy
        1. 11.1.1.1 Minimum Lock Time Calculation Example
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 PLL Loop Filter Design
        2. 11.2.2.2 Clock Output Assignment
        3. 11.2.2.3 Calculation Using LCM
        4. 11.2.2.4 Device Programming
        5. 11.2.2.5 Device Selection
        6. 11.2.2.6 Clock Architect
      3. 11.2.3 Application Curves
    3. 11.3 Do's and Don'ts
      1. 11.3.1 Pin Connection Recommendations
  12. 12Power Supply Recommendations
    1. 12.1 Recommended Power Supply Connection
    2. 12.2 Current Consumption / Power Dissipation Calculations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 CLKin and OSCin
      2. 13.1.2 CLKout
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 デバイス・サポート
      1. 14.1.1 開発サポート
        1. 14.1.1.1 クロック設計ツール
        2. 14.1.1.2 Clock Architect
        3. 14.1.1.3 TICS Pro
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報

10.3.5.1 PLL1

PLL1 in LMK0461x is a very low bandwidth PLL. The PLL is a fully programmable, ultra-flexible design and is intended to be used for jitter cleaning of the noisy input clock. The PLL uses a semi-digital architecture and there is no need for external loop filter. The loop-filter has separated integral and proportional paths, which can be programmed individually to define the PLL transfer. There is a possibility to add higher order poles by connecting a capacitor outside the chip with a fixed on-chip resistor RCTRL. The block diagram of the PLL1 is shown in Figure 36. The PLL uses an external VCXO as a voltage controlled oscillator. Both positive and negative gain VCXOs are supported by LMK046xx.

LMK04610 PLL1_p_LMK04610.gifFigure 36. PLL1 Block Diagram

To reduce lock time, PLL1 supports two locking modes which can be individually configured by the user. When configured, PLL1 starts with Fastlock (with very high integral gain) and after lock, it switches to desired integral gain.

PLL1 Bandwidth depends on the VCXO gain and loop parameters. LMK0461x PLLs are designed with active damping technique. For a given VCXO gain and divider settings, the bandwidth can be programmed by using the PLL1_PROP settings. The higher the value, the higher the bandwidth.

Table 13 shows the internal PLL1 parameter, register and programming ranges. Use the TICS Pro EVM tool to calculate PLL1_PROP, PLL1_PROP_LF, PLL1_INTG, and PLL1_INTG_LF values.

Table 13. PLL1 Parameter and Register

PARAMETER REGISTER DESCRIPTION MIN TYP MAX UNIT
CLKINx_PLL1_RDIV 0x1B,0x1C,0X1D,0x1E, 0x1F,0x20,0x21,0x22 Input clock divider for PLL1 1 32771
PLL1_NDIV 0x61,0x62 Feedback clock divider for PLL1 1 32771
PLL1_PROP 0x5A Proportional gain setting 0 127
PLL1_PROP_FL 0x5B Proportional gain setting for Fast Lock 0 127
PLL1_INTG 0x59 Integral gain setting 0 0 15
PLL1_INTG_FL 0x59 Integral gain setting for Fast Lock 0 15 15
RCTRL 500 Ω