JAJSCZ3A March   2017  – February 2018 LM25141-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High Voltage Start-Up Regulator
      2. 8.3.2  VCC Regulator
      3. 8.3.3  Oscillator
      4. 8.3.4  Synchronization
      5. 8.3.5  Frequency Dithering (Spread Spectrum)
      6. 8.3.6  Enable
      7. 8.3.7  Power Good
      8. 8.3.8  Output Voltage
        1. 8.3.8.1 Minimum Output Voltage Adjustment
      9. 8.3.9  Current Sense
      10. 8.3.10 DCR Current Sensing
      11. 8.3.11 Error Amplifier and PWM Comparator
      12. 8.3.12 Slope Compensation
      13. 8.3.13 Hiccup Mode Current Limiting
      14. 8.3.14 Standby Mode
      15. 8.3.15 Soft Start
      16. 8.3.16 Diode Emulation
      17. 8.3.17 High- and Low-Side Drivers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Inductor Calculation
        3. 9.2.2.3 Current Sense Resistor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Input Filter
          1. 9.2.2.5.1 EMI Filter Design
          2. 9.2.2.5.2 MOSFET Selection
          3. 9.2.2.5.3 Driver Slew Rate Control
          4. 9.2.2.5.4 Frequency Dithering
        6. 9.2.2.6 Control Loop
          1. 9.2.2.6.1 Feedback Compensator
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Procedure
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
        1. 12.2.1.1 PCBレイアウトについてのリソース
        2. 12.2.1.2 熱設計についてのリソース
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

9.2.2.6 Control Loop

The open-loop gain is defined as the product of modulator transfer function and feedback transfer function. When plotted on a dB scale, the open-loop gain is shown as the sum of modulator gain and feedback gain.

DC modulator gain is:

Equation 49. LM25141-Q1 equation_48_snvsaj6.gif

The modulator gain plus power stage transfer function with an embedded current loop is show in Equation 50. The Equation 50 includes the sample gain at FSW /2 (ωn), which is caused by sampling effect of current mode control.

Equation 50. LM25141-Q1 equation_49_snvsaj6.gif

where

  • s = 2 × π × FSW
  • LM25141-Q1 equation_50_snvsaj6.gif
  • LM25141-Q1 equation_51_snvsaj6.gif
  • LM25141-Q1 equation_52_snvsaj6.gif

    LM25141-Q1 equation_53_snvsaj6.gif
  • K = 1
  • GCS is the current sense amplifier gain which is 12

Because the loop cross over frequency is well below sample gain effects, Equation 50 can be simplified as one pole and a one zero system as shown in Equation 51.

Equation 51. LM25141-Q1 equation_54_snvsaj6.gif

RLOAD is the load resistance

RDCR is the DC resistance on the output inductor which is 8.1 mΩ

RSENSE is the current sense resistance which is 9 mΩ