JAJSD07C September   2016  – December 2022 DS90UB934-Q1

PRODUCTION DATA  

  1.   特長
  2. 1アプリケーション
  3. 2概要
  4. 3Revision History
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Electrical Characteristics
    6. 4.6 AC Electrical Characteristics
    7. 4.7 Recommended Timing for the Serial Control Bus
    8. 4.8 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Serial Frame Format
      2. 5.3.2 Line Rate Calculations for the DS90UB933/934
      3. 5.3.3 Deserializer Multiplexer Input
    4. 5.4 Device Functional Modes
      1. 5.4.1 RX MODE Pin
      2. 5.4.2 DVP Output Control
        1. 5.4.2.1 LOCK Status
      3. 5.4.3 Input Jitter Tolerance
      4. 5.4.4 Adaptive Equalizer
      5. 5.4.5 Channel Monitor Loop-Through Output Driver
        1. 5.4.5.1 Code Example for CMLOUT FPD3 RX Port 0:
      6. 5.4.6 GPIO Support
        1. 5.4.6.1 Back Channel GPIO
        2. 5.4.6.2 GPIO Pin Status
        3. 5.4.6.3 Other GPIO Pin Controls
        4. 5.4.6.4 FrameSync Operation
          1. 5.4.6.4.1 External FrameSync Control
          2. 5.4.6.4.2 Internally Generated FrameSync
            1. 5.4.6.4.2.1 Code Example for Internally Generated FrameSync
    5. 5.5 Programming
      1. 5.5.1 Serial Control Bus
        1. 5.5.1.1 I2C Target Operation
        2. 5.5.1.2 Remote Target Operation
        3. 5.5.1.3 Remote I2C Targets Data Throughput
        4. 5.5.1.4 Remote Target Addressing
        5. 5.5.1.5 Broadcast Write to Remote Target Devices
        6. 5.5.1.6 Code Example for Broadcast Write
      2. 5.5.2 Interrupt Support
        1. 5.5.2.1 Code Example to Enable Interrupts
        2. 5.5.2.2 FPD-Link III Receive Port Interrupts
        3. 5.5.2.3 Code Example to Readback Interrupts
        4. 5.5.2.4 Built-In Self Test (BIST)
          1. 5.5.2.4.1 BIST Configuration and Status
    6. 5.6 Register Maps
      1. 5.6.1 Register Description
      2. 5.6.2 Registers
      3. 5.6.3 Indirect Access Registers
      4. 5.6.4 Indirect Access Register Map
        1. 5.6.4.1 FPD3 Channel 0 Registers
        2. 5.6.4.2 FPD3 Channel 1 Registers
        3. 5.6.4.3 FPD3 RX Shared Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Power Over Coax
    3. 6.3 Typical Application
      1. 6.3.1 Design Requirements
      2. 6.3.2 Detailed Design Procedure
      3. 6.3.3 Application Curves
    4. 6.4 System Examples
    5. 6.5 Power Supply Recommendations
      1. 6.5.1 VDD Power Supply
      2. 6.5.2 Power-Up Sequencing
      3. 6.5.3 PDB Pin
      4. 6.5.4 Ground
    6. 6.6 Layout
      1. 6.6.1 Layout Guidelines
        1. 6.6.1.1 DVP Interface Guidelines
      2. 6.6.2 Layout Example
  9.   Mechanical, Packaging, and Orderable Information
  10. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Glossary
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 サポート・リソース
    5. 7.5 Trademarks
  11.   Mechanical, Packaging, and Orderable Information

5.5.1 Serial Control Bus

The DS90UB934-Q1 implements an I2C-compatible serial control bus. The I2C is for local device configuration and incorporates a bidirectional control channel (BCC) that allows communication with a remote serializers as well as remote I2C target devices.

The device address is set via a resistor divider (RHIGH and RLOW — see Figure 5-6) connected to the IDX pin.

GUID-FBC59529-CC55-41FE-A45F-747B59F0366D-low.gifFigure 5-6 Serial Control Bus Connection

The serial control bus consists of two signals, SCL and SDA. SCL is a serial bus clock input. SDA is the serial bus data input/output signal. Both SCL and SDA signals require an external pullup resistor to 1.8-V or 3.3-V V(VI2C). The pullup resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled high or driven low.

The IDX pin configures the control interface to one of 8 possible device addresses. A pullup resistor and a pulldown resistor may be used to set the appropriate voltage ratio between the IDX input pin (V(IDX)) and V(VI2C), each ratio corresponding to a specific device address (see Table 5-7).

Table 5-7 Serial Control Bus Addresses for IDX
VIDX VOLTAGE RANGEVIDX TARGET VOLTAGESUGGESTED STRAP RESISTORS (1% TOL)ASSIGNED I2C ADDRESS
NO.VMINVTYPVMAX(V); V(VDD18) = 1.8 VRHIGH (kΩ )RLOW (kΩ )7-BIT8-BIT
0000.131 × V(VDD18)0OPEN10.00x300x60
10.179 × V(VDD18)0.213 × V(VDD18)0.247 × V(VDD18)0.37488.723.20x320x64
20.296 × V(VDD18)0.330 × V(VDD18)0.362 × V(VDD18)0.58275.035.70x340x68
30.412 × V(VDD18)0.443 × V(VDD18)0.474 × V(VDD18)0.79271.556.20x360x6C
40.525 × V(VDD18)0.559 × V(VDD18)0.592 × V(VDD18)0.99578.797.60x380x70
50.642 × V(VDD18)0.673 × V(VDD18)0.704 × V(VDD18)1.20239.278.70x3A0x74
60.761 × V(VDD18)0.792 × V(VDD18)0.823 × V(VDD18)1.42025.595.30x3C0x78
70.876 × V(VDD18)V(VDD18)V(VDD18)1.810OPEN0x3D0x7A

The serial bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SDA transitions low while SCL is high. A STOP occurs when SDA transitions high while SCL is also high. See Figure 5-7.

GUID-978612F7-8A74-4B27-BE17-1DDD23327CD5-low.gifFigure 5-7 START and STOP Conditions

To communicate with a remote device, the host controller (controller) sends the target address and listens for a response from the target. This response is referred to as an acknowledge bit (ACK). If a target on the bus is addressed correctly, it acknowledges (ACKs) the controller by driving the SDA bus low. If the address does not match the target address of a device, it not-acknowledges (NACKs) the controller by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the controller is writing data, the target ACKs after every data byte is successfully received. When the controller is reading data, the controller ACKs after every data byte is received to let the target know it wants to receive another data byte. When the controller wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a START condition or a REPEATED-START condition. All communication on the bus ends with a STOP condition. A READ is shown in Figure 5-8 and a WRITE is shown in Figure 5-9.

GUID-20221121-SS0I-KX7H-WBRF-X2D7X2BGFZD8-low.gif Figure 5-8 Serial Control Bus — READ
GUID-20221121-SS0I-24XC-RSWQ-557D6G6M5KXP-low.gif Figure 5-9 Serial Control Bus — WRITE
GUID-66342DFE-CD7A-4A73-9073-78BC10B1CFEA-low.gifFigure 5-10 Basic Operation

The I2C controller located at the deserializer must support I2C clock stretching. For more information on I2C interface requirements and throughput considerations, refer to AN-2173 I2C Communication Over FPD-Link III with Bidirectional Control Channel (SNLA131).