JAJSD90 データシート

JAJSD90D June 2017 – August 2021 LM5176

PRODUCTION DATA

6.5 Electrical Characteristics

Typical values correspond to T_J = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature range unless otherwise stated. V_IN = 24 V unless otherwise stated.⁽¹⁾

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (V_IN)
I_Q	V_IN shutdown current	V_EN/UVLO = 0 V		2.6	10	µA
	V_IN operating current	V_EN/UVLO = 2 V, V_FB = 0.9 V		2	4	mA
VCC
V_VCC(VIN)	Regulation voltage	V_BIAS = 0 V, VCC open	6.95	7.35	7.88	V
V_UV(VCC)	VCC undervoltage lockout	VCC increasing	3.11	3.27	3.43	V
	Undervoltage hysteresis			176		mV
I_VCC	VCC current limit	V_VCC = 0 V	65			mA
R_OUT(VCC)	VCC regulator output impedance	I_VCC = 30 mA, V_IN = 4 V		8	16	Ω
BIAS
V_BIAS(SW)	BIAS switchover voltage	V_IN = 24 V	7.25	8	8.75	V
EN/UVLO
V_EN(STBY)	Standby threshold	EN/UVLO rising	0.55	0.82	0.97	V
I_EN(STBY)	Standby source current	V_EN/UVLO = 1.1 V	1	2	3	µA
V_EN(OP)	Operating threshold	EN/UVLO rising	1.17	1.22	1.29	V
ΔI_HYS(OP)	Operating hysteresis current	V_EN/UVLO = 1.5 V	2.15	3.15	4.25	µA
SS
I_SS	Soft-start pullup current	V_SS = 0 V	3.75	5	6.35	µA
V_SS(CL)	SS clamp voltage	SS open		1.21		V
V_FB - V_SS	FB to SS offset	V_SS = 0 V		–18		mV
EA (ERROR AMPLIFIER)
V_REF	Feedback reference voltage	FB = COMP	0.788	0.800	0.812	V
gm_EA	Error amplifier gm			1.31		mS
I_SINK/I_SOURCE	COMP sink/source current	V_FB=V_REF ± 300 mV		280		µA
R_OUT	Amplifier output resistance			20		MΩ
BW	Unity gain bandwidth			2		MHz
I_BIAS(FB)	Feedback pin input bias current	FB in regulation			25	nA
FREQUENCY
f_SW(1)	Switching frequency 1	RT = 40 kΩ	175	200	225	kHz
f_SW(2)	Switching frequency 2	RT = 20 kΩ	350	390	430	kHz
DITHER
I_DITHER	Dither source/sink current			11		µA
V_DITHER	Dither high threshold			1.27		V
V_DITHER	Dither low threshold			1.16		V
SYNC
V_SYNC	Sync input high threshold		2.1			V
V_SYNC	Sync input low threshold				1.2	V
PW_SYNC	Minimum sync input pulse width		50			ns
CURRENT LIMIT
V_CS(BUCK)	Buck current limit threshold (Valley, HTSSOP-28)	V_IN = V_VISNS = 24 V, V_VOSNS = 12 V, V_SLOPE = 0 V	66	80	94	mV
	Buck current limit threshold (Valley, QFN-28)	V_IN = V_VISNS = 24 V, V_VOSNS = 12 V, V_SLOPE = 0 V	60	80	94	mV
V_CS(BOOST)	Boost current limit threshold (Peak, HTSSOP-28)	V_IN = V_VISNS = 12 V, V_VOSNS = 18 V, V_SLOPE = 0 V	100	120	140	mV
	Boost current limit threshold (Peak, QFN-28)	V_IN = V_VISNS = 12 V, V_VOSNS = 18 V, V_SLOPE = 0 V	96	120	140	mV
I_BIAS(CS/CSG)	CS/CSG pin bias current	V_CS = V_CSG = 0 V		-80		µA
I_{OFFSET(CS/CSG)}	CSG pin bias current	V_CS = V_CSG = 0 V			19	µA
CONSTANT CURRENT LOOP
V_SNS	Average current loop regulation target	V_ISNS(-) = 24 V, sweep ISNS(+), V_SS = 0.8 V	43	50	57	mV
I_SNS	ISNS(+), ISNS(–) pin bias currents	V_ISNS(+) = V_ISNS(–) = V_IN = 24 V		3		µA
Gm	gm of soft-start pulldown amplifier	V_ISNS(+)–V_ISNS(–) = 55 mV, V_SS = 0.5 V		1		mS
SLOPE
I_SLOPE	Buck adaptive slope current	V_IN = V_VISNS = 24 V, V_VOSNS = 12 V, V_SLOPE = 0 V	24	30	35	µA
I_SLOPE	Boost adaptive slope current	V_IN = V_VISNS = 12 V, V_VOSNS = 18 V, V_SLOPE = 0 V	13	17	21	µA
gm_SLOPE	Slope compensation amplifier gm			2		µS
MODE
I_MODE	Source current out of MODE pin		17	20	23	µA
V_{CCM_HIC}	CCM with hiccup threshold		1.18	1.28	1.38	V
V_CCM	CCM no hiccup threshold		2.22	2.4	2.6	V
PGOOD
V_PGD	PGOOD trip threshold for falling FB	Measured with respect to V_REF		–9%
V_PGD	PGOOD trip threshold for rising FB	Measured with respect to V_REF		10%
	Hysteresis			2.5%
I_LEAK(PGD)	PGOOD leakage current				100	nA
I_SINK(PGD)	PGOOD sink current	V_PGOOD = 0.4 V	2	4.2	6.5	mA
OUTPUT OVP
V_OVP	Output overvoltage threshold at FB pin	Measured with respect to V_REF		10%
	Hysteresis			2.5%
NMOS DRIVERS
I_HDRV1,2	Driver peak source current	V_BOOT - V_SW = 7 V		1.8		A
I_HDRV1,2	Driver peak sink current	V_BOOT - V_SW = 7 V		2.2		A
I_LDRV1,2	Driver peak source current			1.8		A
I_LDRV1,2	Driver peak sink current			2.2		A
R_HDRV1,2	Driver pullup resistance	V_BOOT - V_SW = 7 V		1.8		Ω
R_HDRV1,2	Driver pulldown resistance	V_BOOT - V_SW = 7 V		1.1		Ω
V_UV(BOOT1,2)	BOOT1,2 to SW1,2 UVLO threshold	HDRV1,2 shut off		3.4		V
	BOOT1,2 to SW1,2 UVLO hysteresis	HDRV1,2 start switching		150		mV
R_LDRV1,2	Driver pullup resistance			1.7		Ω
R_LDRV1,2	Driver pulldown resistance			1.3		Ω
t_DT1	Dead time HDRV1,2 off to LDRV1,2 on			45		ns
t_DT2	Dead time LDRV1,2 off to HDRV1,2 on			45		ns
THERMAL SHUTDOWN
T_SD	Thermal shutdown temperature			165		°C
T_SD(HYS)	Thermal shutdown hysteresis			15		°C

(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.