JAJSD90D June   2017  – August 2021 LM5176

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation
      2. 7.3.2  VCC Regulator and Optional BIAS Input
      3. 7.3.3  Enable/UVLO
      4. 7.3.4  Soft Start
      5. 7.3.5  Overcurrent Protection
      6. 7.3.6  Average Input/Output Current Limiting
      7. 7.3.7  Operation Above 40-V Input
      8. 7.3.8  CCM Operation
      9. 7.3.9  Frequency and Synchronization (RT/SYNC)
      10. 7.3.10 Frequency Dithering
      11. 7.3.11 Output Overvoltage Protection (OVP)
      12. 7.3.12 Power Good (PGOOD)
      13. 7.3.13 Gm Error Amplifier
      14. 7.3.14 Integrated Gate Drivers
      15. 7.3.15 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown, Standby, and Operating Modes
      2. 7.4.2 MODE Pin Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH Tools
        2. 8.2.2.2  Frequency
        3. 8.2.2.3  VOUT
        4. 8.2.2.4  Inductor Selection
        5. 8.2.2.5  Output Capacitor
        6. 8.2.2.6  Input Capacitor
        7. 8.2.2.7  Sense Resistor (RSENSE)
        8. 8.2.2.8  Slope Compensation
        9. 8.2.2.9  UVLO
        10. 8.2.2.10 Soft-Start Capacitor
        11. 8.2.2.11 Dither Capacitor
        12. 8.2.2.12 MOSFETs QH1 and QL1
        13. 8.2.2.13 MOSFETs QH2 and QL2
        14. 8.2.2.14 Frequency Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design with WEBENCH Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.3.3 Enable/UVLO

The LM5176 has a dual function enable and undervoltage lockout (UVLO) circuit. The EN/UVLO pin has three distinct voltage ranges: shutdown, standby, and operating (see Section 7.4.1). When the EN/UVLO pin is below the standby threshold, VEN(STBY), the converter is held in a low power shutdown mode. When EN/UVLO voltage is greater than the standby threshold, VEN(STBY), but less than the operating threshold, VEN(OP), the internal bias rails and the VCC regulator are enabled but the soft-start (SS) pin is held low and the PWM controller is disabled. A pullup current IEN(STBY) is sourced out of the EN/UVLO pin in standby mode to provide hysteresis between the shutdown mode and the standby mode. When EN/UVLO is greater than the operating threshold, VEN(OP), and VCC is above the undervoltage threshold, VUV(VCC), the controller starts operation. A hysteresis current ΔIHYS(OP) is sourced out of the EN/UVLO pin when the EN/UVLO input exceeds the operating threshold to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly changing input voltage.

The VIN UVLO threshold is typically set by a resistor divider from VIN to AGND (Figure 7-2). The turnon threshold VIN(UV) is calculated using Equation 1 where RUV2 is the upper resistor and RUV1 is the lower resistor in the EN/UVLO resistor divider:

Equation 1. GUID-3CAE7159-9B63-4C18-B7D3-97B7505ACC02-low.gif

The hysteresis between the UVLO turnon threshold and turnoff threshold is set by the upper resistor in the EN/UVLO resistor divider and is given by:

Equation 2. GUID-201182A0-7BAA-48CD-B4EF-ED320C3479C9-low.gif
GUID-FDA986A6-6561-4F35-8F17-D7FF99911002-low.gifFigure 7-2 UVLO Threshold Programming