JAJSDA5B November   2017  – November 2020 LM5145

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Range (VIN)
      2. 8.3.2  Output Voltage Setpoint and Accuracy (FB)
      3. 8.3.3  High-Voltage Bias Supply Regulator (VCC)
      4. 8.3.4  Precision Enable (EN/UVLO)
      5. 8.3.5  Power Good Monitor (PGOOD)
      6. 8.3.6  Switching Frequency (RT, SYNCIN)
        1. 8.3.6.1 Frequency Adjust
        2. 8.3.6.2 Clock Synchronization
      7. 8.3.7  Configurable Soft Start (SS/TRK)
        1. 8.3.7.1 Tracking
      8. 8.3.8  Voltage-Mode Control (COMP)
      9. 8.3.9  Gate Drivers (LO, HO)
      10. 8.3.10 Current Sensing and Overcurrent Protection (ILIM)
      11. 8.3.11 OCP Duty Cycle Limiter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Diode Emulation Mode
      5. 8.4.5 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design and Implementation
      2. 9.1.2 Power Train Components
        1. 9.1.2.1 Inductor
        2. 9.1.2.2 Output Capacitors
        3. 9.1.2.3 Input Capacitors
        4. 9.1.2.4 Power MOSFETs
      3. 9.1.3 Control Loop Compensation
      4. 9.1.4 EMI Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – 20-A High-Efficiency Synchronous Buck Regulator for Telecom Power Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Custom Design With WEBENCH® Tools
        4. 9.2.1.4 Application Curves
      2. 9.2.2 Design 2 – High Density, 12-V, 10-A Rail With LDO Low-Noise Auxiliary Output for RF Power Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Design 3 – 150-W, Regulated 24-V Rail for Commercial Drone Applications With Output Voltage Tracking Feature
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Design 4 – Powering a Multicore DSP From a 24-V or 48-V Rail
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate Drive Layout
      3. 11.1.3 PWM Controller Layout
      4. 11.1.4 Thermal Design and Layout
      5. 11.1.5 Ground Plane Design
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
      3. 12.1.3 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
        1. 12.2.1.1 PCB Layout Resources
        2. 12.2.1.2 Thermal Design Resources
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

9.2.4.2 Detailed Design Procedure

The schematic diagram of a 300-kHz, 24-V nominal input, 10-A regulator powering a KeyStone™ DSP is given in Figure 9-46. This high step-down ratio design leverages the low 40-ns minimum controllable on-time of the LM5145 controller to achieve stable, efficient operation at very low duty cycles. 60-V power MOSFETs, such as TI's CSD18543Q3A and CSD18531Q5A NexFET devices, are used together with a low-DCR, metal-powder inductor, and ceramic output capacitor implementation. An external rail between 8 V and 13 V powers VCC to minimize bias power dissipation, and a blocking diode connected to the VIN pin is used as recommended in Figure 8-2.

The important components for this design are listed in Table 9-12.

Table 9-12 List of Materials for Application Circuit 4
REFERENCE DESIGNATORQTYSPECIFICATIONMANUFACTURERPART NUMBER
CIN52.2 µF, 100 V, X7R, 1206, ceramicMurataGRM31CR72A225MA73L
SamsungCL31B225KCHSNNE
34.7 µF, 80 V, X7R, 1210, ceramicMurataGRM32ER71K475KE14L
COUT4100 µF, 6.3V, X7S, 1210, ceramicMurataGRM32EC70J107ME15L
Taiyo YudenJMK325AC7107MM-P
100 µF, 6.3V, X5R, 1206, ceramicMurataGRM31CR60J107ME39K
TDKC3216X5R0J107M
Würth Electronik885012108005
LF11 µH, 5.6 mΩ, 16 A, 6.95 × 6.6 × 2.8 mmCyntecCMLE063T-1R0MS
1 µH, 5.5 mΩ, 12 A, 6.65 × 6.45 × 3.0 mmWürth ElectronikWE XHMI 74439344010
1 µH, 7.9 mΩ, 16 A, 6.5 × 6.0 × 3.0 mmPanasonicETQP3M1R0YFN
1 µH, 6.95 mΩ, 18 A, 6.76 × 6.56 × 3.1 mmCoilcraftXEL6030-102ME
Q1160 V, 8.5 mΩ, high-side MOSFET, SON 3 × 3Texas InstrumentsCSD18543Q3A
Q2160 V, 4 mΩ, low-side MOSFET, SON 5 × 6Texas InstrumentsCSD18531Q5A
U11Wide VIN synchronous buck controllerTexas InstrumentsLM5145RGYR
U216- or 4-bit VID voltage programmer, WSON-10Texas InstrumentsLM10011SD
U31KeyStone™ DSPTexas InstrumentsTMS320C667x

The regulator output current requirements are dependent upon the baseline and activity power consumption of the DSP in a real-use case. While baseline power is highly dependent on voltage, temperature and DSP frequency, activity power relates to dynamic core utilization, DDR3 memory access, peripherals, and so on. To this end, the IDAC_OUT pin of the LM10011 connects to the LM5145 FB pin to allow continuous optimization of the core voltage. The SmartReflex-enabled DSP provides 6-bit information using the VCNTL open-drain I/Os to command the output voltage setpoint with 6.4-mV step resolution.(1)