JAJSDA5B November   2017  – November 2020 LM5145

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Range (VIN)
      2. 8.3.2  Output Voltage Setpoint and Accuracy (FB)
      3. 8.3.3  High-Voltage Bias Supply Regulator (VCC)
      4. 8.3.4  Precision Enable (EN/UVLO)
      5. 8.3.5  Power Good Monitor (PGOOD)
      6. 8.3.6  Switching Frequency (RT, SYNCIN)
        1. 8.3.6.1 Frequency Adjust
        2. 8.3.6.2 Clock Synchronization
      7. 8.3.7  Configurable Soft Start (SS/TRK)
        1. 8.3.7.1 Tracking
      8. 8.3.8  Voltage-Mode Control (COMP)
      9. 8.3.9  Gate Drivers (LO, HO)
      10. 8.3.10 Current Sensing and Overcurrent Protection (ILIM)
      11. 8.3.11 OCP Duty Cycle Limiter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Diode Emulation Mode
      5. 8.4.5 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design and Implementation
      2. 9.1.2 Power Train Components
        1. 9.1.2.1 Inductor
        2. 9.1.2.2 Output Capacitors
        3. 9.1.2.3 Input Capacitors
        4. 9.1.2.4 Power MOSFETs
      3. 9.1.3 Control Loop Compensation
      4. 9.1.4 EMI Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – 20-A High-Efficiency Synchronous Buck Regulator for Telecom Power Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Custom Design With WEBENCH® Tools
        4. 9.2.1.4 Application Curves
      2. 9.2.2 Design 2 – High Density, 12-V, 10-A Rail With LDO Low-Noise Auxiliary Output for RF Power Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Design 3 – 150-W, Regulated 24-V Rail for Commercial Drone Applications With Output Voltage Tracking Feature
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Design 4 – Powering a Multicore DSP From a 24-V or 48-V Rail
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate Drive Layout
      3. 11.1.3 PWM Controller Layout
      4. 11.1.4 Thermal Design and Layout
      5. 11.1.5 Ground Plane Design
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
      3. 12.1.3 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
        1. 12.2.1.1 PCB Layout Resources
        2. 12.2.1.2 Thermal Design Resources
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

9.2.3.3 Application Curves

GUID-B9CEBA85-D27E-4ADC-8B05-B2FADBCD0B18-low.gif
 
Figure 9-34 Efficiency vs IOUT and VIN
GUID-759E6484-526E-469F-B0BB-ED867BB7C00A-low.gif
VIN ramped to 60 V 5-Ω Load
Figure 9-36 Start-Up, 5-A Resistive Load
GUID-DAFFE504-CA0A-44F2-88CB-3F57D3218CC0-low.gif
VIN = 60 V 5-Ω Load
Figure 9-38 ENABLE ON, 5-A Resistive Load
GUID-25F15E0C-1715-40F0-926D-DB10740119E1-low.gif
VIN = 48 V
Figure 9-40 Load Transient Response, 2.5 A to 5 A to 2.5 A
GUID-AFED124B-AB96-4D48-8676-A6D5C6A911CB-low.gif
IOUT = 5 A
Figure 9-42 Line Transient Response, 48 V to 85 V
GUID-10452BC3-4E70-4D54-8EB7-0802BA5E0F87-low.gif
VIN = 60 V IOUT = 0 A
Figure 9-44 Pre-Biased Start-Up
GUID-25BA9DD4-F5FB-4CCD-B608-BA952CD1666D-low.gif
VIN = 48 V IOUT = 5 A
Figure 9-35 SW Node and SYNCOUT Voltages
GUID-B82ADA1C-888F-4AE9-98F1-3B62682042F1-low.gif
VIN 85 V to 48 V 5-Ω Load
Figure 9-37 Shutdown Through Input UVLO, 5-A Resistive Load
GUID-E4BBDBB3-3263-47E2-A12D-DC01D46F490B-low.gif
VIN = 60 V 5-Ω Load
Figure 9-39 ENABLE OFF, 10-A Resistive Load
GUID-8E964779-4237-4E19-A452-E504A5CAD1CB-low.gif
VIN = 48 V
Figure 9-41 Load Transient Response, 0 A to 5 A to 0 A
GUID-BC7AD13D-154D-4A54-8986-60CF5EDD9D06-low.gif
IOUT = 5 A
Figure 9-43 Line Transient Response, 85 V to 48 V
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VIN = 48 V IOUT = 0 A
Figure 9-45 SW Node and SYNCIN Voltages at 600 kHz