JAJSDA5B November   2017  – November 2020 LM5145

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Range (VIN)
      2. 8.3.2  Output Voltage Setpoint and Accuracy (FB)
      3. 8.3.3  High-Voltage Bias Supply Regulator (VCC)
      4. 8.3.4  Precision Enable (EN/UVLO)
      5. 8.3.5  Power Good Monitor (PGOOD)
      6. 8.3.6  Switching Frequency (RT, SYNCIN)
        1. 8.3.6.1 Frequency Adjust
        2. 8.3.6.2 Clock Synchronization
      7. 8.3.7  Configurable Soft Start (SS/TRK)
        1. 8.3.7.1 Tracking
      8. 8.3.8  Voltage-Mode Control (COMP)
      9. 8.3.9  Gate Drivers (LO, HO)
      10. 8.3.10 Current Sensing and Overcurrent Protection (ILIM)
      11. 8.3.11 OCP Duty Cycle Limiter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Diode Emulation Mode
      5. 8.4.5 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design and Implementation
      2. 9.1.2 Power Train Components
        1. 9.1.2.1 Inductor
        2. 9.1.2.2 Output Capacitors
        3. 9.1.2.3 Input Capacitors
        4. 9.1.2.4 Power MOSFETs
      3. 9.1.3 Control Loop Compensation
      4. 9.1.4 EMI Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – 20-A High-Efficiency Synchronous Buck Regulator for Telecom Power Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Custom Design With WEBENCH® Tools
        4. 9.2.1.4 Application Curves
      2. 9.2.2 Design 2 – High Density, 12-V, 10-A Rail With LDO Low-Noise Auxiliary Output for RF Power Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Design 3 – 150-W, Regulated 24-V Rail for Commercial Drone Applications With Output Voltage Tracking Feature
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Design 4 – Powering a Multicore DSP From a 24-V or 48-V Rail
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate Drive Layout
      3. 11.1.3 PWM Controller Layout
      4. 11.1.4 Thermal Design and Layout
      5. 11.1.5 Ground Plane Design
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
      3. 12.1.3 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
        1. 12.2.1.1 PCB Layout Resources
        2. 12.2.1.2 Thermal Design Resources
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

9.2.2.2 Detailed Design Procedure

A high power density, high-efficiency regulator solution uses TI NexFET™ Power MOSFETs, such as CSD18563Q5A (60-V, 6-mΩ MOSFET in a SON 5-mm × 6-mm package), together with a low-DCR inductor and all-ceramic capacitor design. The design occupies 30 mm × 15 mm on a single-sided PCB. The overcurrent (OC) setpoint in this design is set at 14 A based on the resistor RILIM and the 6-mΩ RDS(on) of the low-side MOSFET (typical at TJ = 25°C and VGS = 7.5 V). The 12-V output is connected to VCC through a diode, D1, to reduce IC bias power dissipation.

The selected buck converter powertrain components are cited in Table 9-8, including power MOSFETs, buck inductor, input and output capacitors, and ICs. Use the LM5145 Quickstart Calculator to find compensation components that are selected based on a target loop crossover frequency of 40 kHz and phase margin greater than 55°. The output voltage soft-start time is 4 ms based on the selected soft-start capacitance, CSS, of 33 nF.

Table 9-8 List of Materials for Application Circuit 2
REFERENCE DESIGNATORQTYSPECIFICATIONMANUFACTURERPART NUMBER
CIN54.7 µF, 100 V, X7S, 1210, ceramicTDKC3225X7S2A475M
MurataGRM32DC72A475KE01L
Taiyo YudenHMK325C7475MN-TE
COUT547 µF, 16 V, X5R, 1210, ceramicMurataGRM32ER61C476KE15K
Würth Electronik885012109011
722 µF, 25 V, X7R, 1210, ceramicMurataGRM32ER71E226KE15L
Taiyo YudenTMK325B7226MM-TR
TDKC3225X7R1E226M
LF14.7 µH, 7.8 mΩ, 25 A, 13.45 × 12.6 × 6.3 mmCyntecCMLS136E-4R7MS
4.7 µH, 6.5 mΩ, 27 A, 12.5 × 12.5 × 6.2 mmWürth ElectronikWE-LHMI 744373965047
4.7 µH, 9.75 mΩ, 25 A, 11.3 × 10 × 6 mmCoilcraftXAL1060-472ME
Q1, Q2260 V, 6 mΩ, MOSFET, SON 5 × 6Texas InstrumentsCSD18563Q5A
U11Wide VIN synchronous buck controllerTexas InstrumentsLM5145RGYR
U21Ultra-low noise and high-PSRR LDOTexas InstrumentsLP38798SD-ADJ

As shown in Figure 9-20, a 2.2-Ω resistor in series with CBST is used to slow the turn-on transition of the high-side MOSFET, reducing the spike amplitude and ringing of the SW node voltage and minimizing the possibility of Cdv/dt-induced shoot-through of the low-side MOSFET. If needed, place an RC snubber (for example, 2.2 Ω and 100 pF) close to the drain (SW node) and source (PGND) terminals of the low-side MOSFET to further attenuate any SW node voltage overshoot and/or ringing. Please refer to the application note Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics for more detail.