JAJSDF7A January   2017  – May 2017 LMK61E0M

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ピン配列と単純なブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  3.3-V LVCMOS Output Characteristics
    7. 6.7  OE Input Characteristics
    8. 6.8  ADD Input Characteristics
    9. 6.9  Frequency Tolerance Characteristics
    10. 6.10 Frequency Margining Characteristics
    11. 6.11 Power-On/Reset Characteristics (VDD)
    12. 6.12 I2C-Compatible Interface Characteristics (SDA, SCL)
    13. 6.13 Other Characteristics
    14. 6.14 PLL Clock Output Jitter Characteristics
    15. 6.15 Additional Reliability and Qualification
    16. 6.16 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Block-Level Description
      2. 8.3.2  Device Configuration Control
      3. 8.3.3  Register File Reference Convention
      4. 8.3.4  Configuring the PLL
      5. 8.3.5  Integrated Oscillator
      6. 8.3.6  Reference Divider and Doubler
      7. 8.3.7  Phase Frequency Detector
      8. 8.3.8  Feedback Divider (N)
      9. 8.3.9  Fractional Engine
      10. 8.3.10 Charge Pump
      11. 8.3.11 Loop Filter
      12. 8.3.12 VCO Calibration
      13. 8.3.13 High-Speed Output Divider
      14. 8.3.14 High-Speed Clock Output
      15. 8.3.15 Device Status
        1. 8.3.15.1 Loss of Lock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Interface and Control
      2. 8.4.2 DCXO Mode and Frequency Margining
        1. 8.4.2.1 DCXO Mode
        2. 8.4.2.2 Fine Frequency Margining
        3. 8.4.2.3 Coarse Frequency Margining
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Block Register Write
      3. 8.5.3 Block Register Read
      4. 8.5.4 Write SRAM
      5. 8.5.5 Write EEPROM
      6. 8.5.6 Read SRAM
      7. 8.5.7 Read EEPROM
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  VNDRID_BY1 Register; R0
        2. 8.6.1.2  VNDRID_BY0 Register; R1
        3. 8.6.1.3  PRODID Register; R2
        4. 8.6.1.4  REVID Register; R3
        5. 8.6.1.5  SLAVEADR Register; R8
        6. 8.6.1.6  EEREV Register; R9
        7. 8.6.1.7  DEV_CTL Register; R10
        8. 8.6.1.8  XO_CAPCTRL_BY1 Register; R16
        9. 8.6.1.9  XO_CAPCTRL_BY0 Register; R17
        10. 8.6.1.10 CMOSCTL Register; R20
        11. 8.6.1.11 DIFFCTL Register; R21
        12. 8.6.1.12 OUTDIV_BY1 Register; R22
        13. 8.6.1.13 OUTDIV_BY0 Register; R23
        14. 8.6.1.14 RDIVCMOSCTL Register; R24
        15. 8.6.1.15 PLL_NDIV_BY1 Register; R25
        16. 8.6.1.16 PLL_NDIV_BY0 Register; R26
        17. 8.6.1.17 PLL_FRACNUM_BY2 Register; R27
        18. 8.6.1.18 PLL_FRACNUM_BY1 Register; R28
        19. 8.6.1.19 PLL_FRACNUM_BY0 Register; R29
        20. 8.6.1.20 PLL_FRACDEN_BY2 Register; R30
        21. 8.6.1.21 PLL_FRACDEN_BY1 Register; R31
        22. 8.6.1.22 PLL_FRACDEN_BY0 Register; R32
        23. 8.6.1.23 PLL_MASHCTRL Register; R33
        24. 8.6.1.24 PLL_CTRL0 Register; R34
        25. 8.6.1.25 PLL_CTRL1 Register; R35
        26. 8.6.1.26 PLL_LF_R2 Register; R36
        27. 8.6.1.27 PLL_LF_C1 Register; R37
        28. 8.6.1.28 PLL_LF_R3 Register; R38
        29. 8.6.1.29 PLL_LF_C3 Register; R39
        30. 8.6.1.30 PLL_CALCTRL Register; R42
        31. 8.6.1.31 NVMSCRC Register; R47
        32. 8.6.1.32 NVMCNT Register; R48
        33. 8.6.1.33 NVMCTL Register; R49
        34. 8.6.1.34 MEMADR Register; R51
        35. 8.6.1.35 NVMDAT Register; R52
        36. 8.6.1.36 RAMDAT Register; R53
        37. 8.6.1.37 NVMUNLK Register; R56
        38. 8.6.1.38 INT_LIVE Register; R66
        39. 8.6.1.39 SWRST Register; R72
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 PLL Loop Filter Design
        2. 9.2.2.2 Spur Mitigation Techniques
          1. 9.2.2.2.1 Phase Detection Spur
          2. 9.2.2.2.2 Integer Boundary Fractional Spur
          3. 9.2.2.2.3 Primary Fractional Spur
          4. 9.2.2.2.4 Sub-Fractional Spur
        3. 9.2.2.3 Device Programming
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ensured Thermal Reliability
      2. 11.1.2 Best Practices for Signal Integrity
      3. 11.1.3 Recommended Solder Reflow Profile
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

8.6 Register Maps

Any bit that is labeled as RESERVED should be written with a 0.

Table 2. EEPROM Map

BYTE NO.BIT7BIT6BIT5BIT4BIT3BIT2BIT1BIT0
0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
2 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
3 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
4 NVMSCRC[7] NVMSCRC[6] NVMSCRC[5] NVMSCRC[4] NVMSCRC[3] NVMSCRC[2] NVMSCRC[1] NVMSCRC[0]
5 NVMCNT[7] NVMCNT[6] NVMCNT[5] NVMCNT[4] NVMCNT[3] NVMCNT[2] NVMCNT[1] NVMCNT[0]
6 1 RESERVED RESERVED RESERVED RESERVED 1 RESERVED RESERVED
7 RESERVED RESERVED 1 RESERVED RESERVED RESERVED RESERVED 1
8 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
9 SLAVEADR[7] SLAVEADR[6] SLAVEADR[5] SLAVEADR[4] SLAVEADR[3] RESERVED RESERVED RESERVED
10 EEREV[7] EEREV[6] EEREV[5] EEREV[4] EEREV[3] EEREV[2] EEREV[1] EEREV[0]
11 RESERVED PLL_PDN RESERVED RESERVED RESERVED RESERVED AUTOSTRT RESERVED
14 RESERVED RESERVED RESERVED RESERVED RESERVED 1 RESERVED 1
15 RESERVED XO_CAPCTRL[1] XO_CAPCTRL[0] XO_CAPCTRL[9] XO_CAPCTRL[8] XO_CAPCTRL[7] XO_CAPCTRL[6] XO_CAPCTRL[5]
16 XO_CAPCTRL[4] XO_CAPCTRL[3] XO_CAPCTRL[2] RESERVED RESERVED RESERVED RESERVED RESERVED
19 RESERVED RESERVED OUT0_HIZ CMOS_MUTE RESERVED OUT1_INV OUT0_INV RESERVED
20 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
21 RESERVED RESERVED RESERVED OUT1_HIZ RESERVED RESERVED RESERVED PLL_RDIV
22 PLL_NDIV[11] PLL_NDIV[10] PLL_NDIV[9] PLL_NDIV[8] PLL_NDIV[7] PLL_NDIV[6] PLL_NDIV[5] PLL_NDIV[4]
23 PLL_NDIV[3] PLL_NDIV[2] PLL_NDIV[1] PLL_NDIV[0] PLL_NUM[21] PLL_NUM[20] PLL_NUM[19] PLL_NUM[18]
24 PLL_NUM[17] PLL_NUM[16] PLL_NUM[15] PLL_NUM[14] PLL_NUM[13] PLL_NUM[12] PLL_NUM[11] PLL_NUM[10]
25 PLL_NUM[9] PLL_NUM[8] PLL_NUM[7] PLL_NUM[6] PLL_NUM[5] PLL_NUM[4] PLL_NUM[3] PLL_NUM[2]
26 PLL_NUM[1] PLL_NUM[0] PLL_DEN[21] PLL_DEN[20] PLL_DEN[19] PLL_DEN[18] PLL_DEN[17] PLL_DEN[16]
27 PLL_DEN[15] PLL_DEN[14] PLL_DEN[13] PLL_DEN[12] PLL_DEN[11] PLL_DEN[10] PLL_DEN[9] PLL_DEN[8]
28 PLL_DEN[7] PLL_DEN[6] PLL_DEN[5] PLL_DEN[4] PLL_DEN[3] PLL_DEN[2] PLL_DEN[1] PLL_DEN[0]
29 PLL_
DTHRMODE[1]		 PLL_DTHRMODE[0] PLL_ORDER[1] PLL_ORDER[0] RESERVED RESERVED PLL_D PLL_CP[3]
30 PLL_CP[2] PLL_CP[1] PLL_CP[0] PLL_CP_PHASE_
SHIFT[2]		 PLL_CP_PHASE_
SHIFT[1]		 PLL_CP_PHASE_
SHIFT[0]		 PLL_ENABLE_
C3[2]		 PLL_ENABLE_
C3[1]
31 PLL_ENABLE_
C3[0]		 PLL_LF_R2[7] PLL_LF_R2[6] PLL_LF_R2[5] PLL_LF_R2[4] PLL_LF_R2[3] PLL_LF_R2[2] PLL_LF_R2[1]
32 PLL_LF_R2[0] PLL_LF_C1[2] PLL_LF_C1[1] PLL_LF_C1[0] PLL_LF_R3[6] PLL_LF_R3[5] PLL_LF_R3[4] PLL_LF_R3[3]
33 PLL_LF_R3[2] PLL_LF_R3[1] PLL_LF_R3[0] PLL_LF_C3[2] PLL_LF_C3[1] PLL_LF_C3[0] CMOS_SLEWRATE[1] CMOS_SLEWRATE[0]
34 PRE_DIV OUT_DIV[8] OUT_DIV[7] OUT_DIV[6] OUT_DIV[5] OUT_DIV[4] OUT_DIV[3] OUT_DIV[2]
35 OUT_DIV[1] OUT_DIV[0] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

The default/reset values for each register is specified for LMK61E0.

Table 3. Register Map

NAMEADDRRESETBIT7BIT6BIT5BIT4BIT3BIT2BIT1BIT0
VNDRID_BY1 0 0x10 VNDRID[15:8]
VNDRID_BY0 1 0x0B VNDRID[7:0]
PRODID 2 0x33 PRODID[7:0]
REVID 3 0x00 REVID[7:0]
SLAVEADR 8 0xB0 SLAVEADR[7:1] RESERVED
EEREV 9 0x00 EEREV[7:0]
DEV_CTL 10 0x01 RESERVED PLL_PDN RESERVED ENCAL AUTOSTRT
XO_CAPCTRL_
BY1		 16 0x00 RESERVED XO_CAPCTRL[1:0]
XO_CAPCTRL_
BY0		 17 0x00 XO_CAPCTRL[9:2]
CMOSCTL 20 0x00 RESERVED OUT0_HIZ CMOS_MUTE RESERVED
DIFFCTL 21 0x01 RESERVED OUT1_INV OUT0_INV RESERVED
OUTDIV_BY1 22 0x00 CMOS_SLEWRATE[1:0] PRE_DIV RESERVED OUT_DIV[8]
OUTDIV_BY0 23 0x20 OUT_DIV[7:0]
RDIVCMOSCTL 24 0x00 RESERVED OUT1_HIZ RESERVED PLL_RDIV
PLL_NDIV_BY1 25 0x00 RESERVED PLL_NDIV[11:8]
PLL_NDIV_BY0 26 0x64 PLL_NDIV[7:0]
PLL_FRACNUM_
BY2		 27 0x00 RESERVED PLL_NUM[21:16]
PLL_FRACNUM_
BY1		 28 0x00 PLL_NUM[15:8]
PLL_FRACNUM_
BY0		 29 0x00 PLL_NUM[7:0]
PLL_FRACDEN_
BY2		 30 0x00 RESERVED PLL_DEN[21:16]
PLL_FRACDEN_
BY1		 31 0x00 PLL_DEN[15:8]
PLL_FRACDEN_
BY0		 32 0x00 PLL_DEN[7:0]
PLL_MASHCTRL 33 0x0C RESERVED PLL_DTHRMODE[1:0] PLL_ORDER[1:0]
PLL_CTRL0 34 0x24 RESERVED PLL_D RESERVED PLL_CP[3:0]
PLL_CTRL1 35 0x03 RESERVED PLL_CP_PHASE_SHIFT[2:0] RESERVED PLL_ENABLE_C3[2:0]
PLL_LF_R2 36 0x28 PLL_LF_R2[7:0]
PLL_LF_C1 37 0x00 RESERVED PLL_LF_C1[2:0]
PLL_LF_R3 38 0x00 RESERVED PLL_LF_R3[6:0]
PLL_LF_C3 39 0x00 RESERVED PLL_LF_C3[2:0]
PLL_CALCTRL 42 0x00 RESERVED PLL_CLSDWAIT[1:0] PLL_VCOWAIT[1:0]
NVMSCRC 47 0x00 NVMSCRC[7:0]
NVMCNT 48 0x00 NVMCNT[7:0]
NVMCTL 49 0x10 RESERVED REGCOMMIT NVMCRCERR NVMAUTOCRC NVMCOMMIT NVMBUSY NVMERASE NVMPROG
NVMLCRC 50 0x00 NVMLCRC[7:0]
MEMADR 51 0x00 RESERVED MEMADR[6:0]
NVMDAT 52 0x00 NVMDAT[7:0]
RAMDAT 53 0x00 RAMDAT[7:0]
NVMUNLK 56 0x00 NVMUNLK[7:0]
INT_LIVE 66 0x00 RESERVED LOL CAL
SWRST 72 0x00 RESERVED SWR2PLL RESERVED