JAJSDF7A January 2017 – May 2017 LMK61E0M
PRODUCTION DATA.
The PLL_NDIV_BY0 register is described in the following table.
BIT NO. | FIELD | TYPE | RESET | EEPROM | DESCRIPTION |
---|---|---|---|---|---|
[7:0] | PLL_NDIV[7:0] | RW | 0x32 | Y | PLL N Divider Byte 0. PLL Integer N Divider bits [7:0]. |