JAJSDJ0C February 2013 – September 2021 TAS2505
PRODUCTION DATA
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | SPI_SEL | I | Selects between SPI and I2C digital interface modes; (1 = SPI mode) (0 = I2C mode) |
2 | RST | I | Reset for logic, state machines, and digital filters; asserted LOW. |
3 | AINL | I | Analog single-ended line left input |
4 | AINR | I | Analog single-ended line right input |
5 | NC | O | No Connect (Leave unconnected) |
6 | AVSS | GND | Analog Ground, 0 V |
7 | AVDD | PWR | Analog Core Supply Voltage, 1.5 V to 1.95 V, tied internally to the LDO output |
8 | LDO_SEL | I | Select Pin for LDO; ties to either SPKVDD or SPKVSS |
9 | SPKM | O | Class-D speaker driver inverting output |
10 | SPKVDD | PWR | Class-D speaker driver power supply |
11 | SPKVSS | PWR | Class-D speaker driver power supply ground supply |
12 | SPKP | O | Class-D speaker driver noninverting output |
13 | DIN | I | Audio Serial Data Bus Input Data |
14 | WCLK | I/O | Audio Serial Data Bus Word Clock |
15 | BCLK | I/O | Audio Serial Data Bus Bit Clock |
16 | MCLK | I | Master CLK Input / Reference CLK for CLK Multiplier - PLL (On startup PLLCLK = CLKIN) |
17 | MISO | O | SPI Serial Data Output |
18 | GPIO/DOUT | I/O/Z | GPIO / Audio Serial Bus Output |
19 | SCL/SSZ | I | Either I2C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state |
20 | SDA/MOSI | I | Either I2C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state. |
21 | SCLK | I | Serial clock for SPI interface |
22 | IOVDD | PWR | I/O Power Supply, 1.1 V to 3.6 V |
23 | DVDD | PWR | Digital Power Supply, 1.65 V to 1.95 V |
24 | DVSS | GND | Digital Ground, 0 V |