JAJSDJ0C February   2013  – September 2021 TAS2505

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  I2S/LJF/RJF Timing in Master Mode
    7. 6.7  I2S/LJF/RJF Timing in Slave Mode
    8. 6.8  DSP Timing in Master Mode
    9. 6.9  DSP Timing in Slave Mode
    10. 6.10 I2C Interface Timing
    11. 6.11 SPI Interface Timing
    12. 6.12 Typical Characteristics
      1. 6.12.1 Class D Speaker Driver Performance
      2. 6.12.2 HP Driver Performance
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Audio Analog I/O
      2. 7.3.2 Audio DAC and Audio Analog Outputs
      3. 7.3.3 DAC
      4. 7.3.4 POR
      5. 7.3.5 CLOCK Generation and PLL
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Pins
      2. 7.4.2 Analog Pins
      3. 7.4.3 Multifunction Pins
      4. 7.4.4 Analog Signals
        1. 7.4.4.1 Analog Inputs AINL and AINR
      5. 7.4.5 DAC Processing Blocks — Overview
      6. 7.4.6 Digital Mixing and Routing
      7. 7.4.7 Analog Audio Routing
      8. 7.4.8 5V LDO
      9. 7.4.9 Digital Audio and Control Interface
        1. 7.4.9.1 Digital Audio Interface
        2. 7.4.9.2 Control Interface
          1. 7.4.9.2.1 I2C Control Mode
          2. 7.4.9.2.2 SPI Digital Interface
        3. 7.4.9.3 Device Special Functions
    5. 7.5 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Circuit Configuration With Internal LDO
        1. 8.2.2.1 Design Requirements
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

GUID-09C2F65B-6D6F-4214-9CBB-B98EC42354C8-low.gifFigure 5-1 RGE Package24-Pin VQFNTop View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 SPI_SEL I Selects between SPI and I2C digital interface modes; (1 = SPI mode) (0 = I2C mode)
2 RST I Reset for logic, state machines, and digital filters; asserted LOW.
3 AINL I Analog single-ended line left input
4 AINR I Analog single-ended line right input
5 NC O No Connect (Leave unconnected)
6 AVSS GND Analog Ground, 0 V
7 AVDD PWR Analog Core Supply Voltage, 1.5 V to 1.95 V, tied internally to the LDO output
8 LDO_SEL I Select Pin for LDO; ties to either SPKVDD or SPKVSS
9 SPKM O Class-D speaker driver inverting output
10 SPKVDD PWR Class-D speaker driver power supply
11 SPKVSS PWR Class-D speaker driver power supply ground supply
12 SPKP O Class-D speaker driver noninverting output
13 DIN I Audio Serial Data Bus Input Data
14 WCLK I/O Audio Serial Data Bus Word Clock
15 BCLK I/O Audio Serial Data Bus Bit Clock
16 MCLK I Master CLK Input / Reference CLK for CLK Multiplier - PLL (On startup PLLCLK = CLKIN)
17 MISO O SPI Serial Data Output
18 GPIO/DOUT I/O/Z GPIO / Audio Serial Bus Output
19 SCL/SSZ I Either I2C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state
20 SDA/MOSI I Either I2C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state.
21 SCLK I Serial clock for SPI interface
22 IOVDD PWR I/O Power Supply, 1.1 V to 3.6 V
23 DVDD PWR Digital Power Supply, 1.65 V to 1.95 V
24 DVSS GND Digital Ground, 0 V
(1) I = Input, O = Output, GND = Ground, PWR = Power, Z = High Impedance