JAJSDJ0C February   2013  – September 2021 TAS2505

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  I2S/LJF/RJF Timing in Master Mode
    7. 6.7  I2S/LJF/RJF Timing in Slave Mode
    8. 6.8  DSP Timing in Master Mode
    9. 6.9  DSP Timing in Slave Mode
    10. 6.10 I2C Interface Timing
    11. 6.11 SPI Interface Timing
    12. 6.12 Typical Characteristics
      1. 6.12.1 Class D Speaker Driver Performance
      2. 6.12.2 HP Driver Performance
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Audio Analog I/O
      2. 7.3.2 Audio DAC and Audio Analog Outputs
      3. 7.3.3 DAC
      4. 7.3.4 POR
      5. 7.3.5 CLOCK Generation and PLL
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Pins
      2. 7.4.2 Analog Pins
      3. 7.4.3 Multifunction Pins
      4. 7.4.4 Analog Signals
        1. 7.4.4.1 Analog Inputs AINL and AINR
      5. 7.4.5 DAC Processing Blocks — Overview
      6. 7.4.6 Digital Mixing and Routing
      7. 7.4.7 Analog Audio Routing
      8. 7.4.8 5V LDO
      9. 7.4.9 Digital Audio and Control Interface
        1. 7.4.9.1 Digital Audio Interface
        2. 7.4.9.2 Control Interface
          1. 7.4.9.2.1 I2C Control Mode
          2. 7.4.9.2.2 SPI Digital Interface
        3. 7.4.9.3 Device Special Functions
    5. 7.5 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Circuit Configuration With Internal LDO
        1. 8.2.2.1 Design Requirements
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

6.11 SPI Interface Timing

At 25°C, DVDD = 1.8V
PARAMETERTEST CONDITIONIOVDD=1.8VIOVDD=3.3VUNIT
MINTYPMAXMINTYPMAX
tsckSCLK period (1)10050ns
tsckhSCLK pulse width High5025ns
tscklSCLK pulse width Low5025ns
tleadEnable lead time3020ns
tlagEnable lag time3020ns
tdSequential transfer delay4020ns
taSlave DOUT access time4040ns
tdisSlave DOUT disable time4040ns
tsuDIN data setup time1515ns
thiDIN data hold time1510ns
tv;DOUTDOUT data valid time2518ns
trSCLK rise time44ns
tfSCLK fall time44ns
(1) These parameters are based on characterization and are not tested in production.
GUID-CE52F142-FC4E-4E2A-98DD-CDFFB58335D8-low.gifFigure 6-1 I2S/LJF/RJF Timing in Master Mode
GUID-0000879C-798F-44C6-B0FA-1106704C8AA1-low.gifFigure 6-2 I2S/LJF/RJF Timing in Slave Mode
GUID-020F5B6B-7154-49EC-8C32-9EAFD38E24C0-low.gifFigure 6-3 DSP Timing in Master Mode
GUID-6C4FCACA-8349-467E-8161-A08441AB0D1B-low.gifFigure 6-4 DSP Timing in Slave Mode
GUID-4B55229F-8DA2-4AF9-B304-F50873234A16-low.gifFigure 6-5 I2C Interface Timing
GUID-57CFEB84-05DD-4346-A51C-CD94CEA35FED-low.gifFigure 6-6 SPI Interface Timing Diagram