JAJSDN8C March   2017  – April 2019 LMX2594

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reference Oscillator Input
      2. 8.3.2  Reference Path
        1. 8.3.2.1 OSCin Doubler (OSC_2X)
        2. 8.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 8.3.2.3 Programmable Multiplier (MULT)
        4. 8.3.2.4 Post-R Divider (PLL_R)
        5. 8.3.2.5 State Machine Clock
      3. 8.3.3  PLL Phase Detector and Charge Pump
      4. 8.3.4  N-Divider and Fractional Circuitry
      5. 8.3.5  MUXout Pin
        1. 8.3.5.1 Lock Detect
        2. 8.3.5.2 Readback
      6. 8.3.6  VCO (Voltage-Controlled Oscillator)
        1. 8.3.6.1 VCO Calibration
        2. 8.3.6.2 Determining the VCO Gain
      7. 8.3.7  Channel Divider
      8. 8.3.8  Output Buffer
      9. 8.3.9  Power-Down Modes
      10. 8.3.10 Phase Synchronization
        1. 8.3.10.1 General Concept
        2. 8.3.10.2 Categories of Applications for SYNC
        3. 8.3.10.3 Procedure for Using SYNC
        4. 8.3.10.4 SYNC Input Pin
      11. 8.3.11 Phase Adjust
      12. 8.3.12 Fine Adjustments for Phase Adjust and Phase SYNC
      13. 8.3.13 Ramping Function
        1. 8.3.13.1 Manual Pin Ramping
          1. 8.3.13.1.1 Manual Pin Ramping Example
        2. 8.3.13.2 Automatic Ramping
          1. 8.3.13.2.1 Automatic Ramping Example (Triangle Wave)
      14. 8.3.14 SYSREF
        1. 8.3.14.1 Programmable Fields
        2. 8.3.14.2 Input and Output Pin Formats
          1. 8.3.14.2.1 Input Format for SYNC and SysRefReq Pins
          2. 8.3.14.2.2 SYSREF Output Format
        3. 8.3.14.3 Examples
        4. 8.3.14.4 SYSREF Procedure
      15. 8.3.15 SysRefReq Pin
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Recommended Initial Power-Up Sequence
      2. 8.5.2 Recommended Sequence for Changing Frequencies
      3. 8.5.3 General Programming Requirements
    6. 8.6 Register Maps
      1. 8.6.1  General Registers R0, R1, & R7
        1. Table 24. Field Descriptions
      2. 8.6.2  Input Path Registers
        1. Table 25. Field Descriptions
      3. 8.6.3  Charge Pump Registers (R13, R14)
        1. Table 26. Field Descriptions
      4. 8.6.4  VCO Calibration Registers
        1. Table 27. Field Descriptions
      5. 8.6.5  N Divider, MASH, and Output Registers
        1. Table 28. Field Descriptions
      6. 8.6.6  SYNC and SysRefReq Input Pin Register
        1. Table 29. Field Descriptions
      7. 8.6.7  Lock Detect Registers
        1. Table 30. Field Descriptions
      8. 8.6.8  MASH_RESET
        1. Table 31. Field Descriptions
      9. 8.6.9  SysREF Registers
        1. Table 32. Field Descriptions
      10. 8.6.10 CHANNEL Divider Registers
        1. Table 33. Field Descriptions
      11. 8.6.11 Ramping and Calibration Fields
        1. Table 34. Field Descriptions
      12. 8.6.12 Ramping Registers
        1. 8.6.12.1 Ramp Limits
          1. Table 35. Field Descriptions
        2. 8.6.12.2 Ramping Triggers, Burst Mode, and RAMP0_RST
          1. Table 36. Field Descriptions
        3. 8.6.12.3 Ramping Configuration
          1. Table 37. Field Descriptions
      13. 8.6.13 Readback Registers
        1. Table 38. Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 OSCin Configuration
      2. 9.1.2 OSCin Slew Rate
      3. 9.1.3 RF Output Buffer Power Control
      4. 9.1.4 RF Output Buffer Pullup
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

7.7 Typical Characteristics

LMX2594 D002_SNAS696.gif
fOSC = 100 MHz Jitter = 55.8 fs (100 Hz - 100 MHz)
fPD = 200 MHz
Figure 3. Closed-Loop Phase Noise at 15 GHz
LMX2594 D004_SNAS696.gif
fOSC = 100 MHz Jitter = 46.8 fs (100 Hz - 100 MHz)
fPD = 200 MHz
Figure 5. Closed-Loop Phase Noise at 11 GHz
LMX2594 D001_SNAS696.gif
fOSC = 100 MHz Jitter = 46.87 fs (100 Hz - 100 MHz)
fPD = 200 MHz
Figure 7. Closed-Loop Phase Noise at 8 GHz
LMX2594 D012_SNAS696.gif
fOSC = 100 MHz fOUT = 14 GHz / 4 = 3.5 GHz
fPD = 200 MHz Jitter = 49.4 fs (100 Hz - 100 MHz)
fVCO = 14 GHz
Figure 9. Closed-Loop Phase Noise at 3.5 GHz
LMX2594 D013_SNAS696.gif
The glitches in the plot are due to the inability of the measurement equipment to track the VCO while calibrating.
Figure 11. VCO Ramping 7.5-GHz to 15-GHz Triangle Wave With VCO Calibration
LMX2594 D009_SNAS696.gif
CalTime = 25.2 µs = 1.3 µs (Core) + 9.1 µs (Fcal) +14.8 µs (Ampcal)
fOSC = 200 MHz, fPD = 100 MHz, fVCO = 7.5 GHz - 14 GHz, CHDIV = 2
Figure 13. VCO Calibration With Partial Assist
LMX2594 tc_fpdimpact.gif
fOSC = 200 MHz fVCO = 14.8 GHz
Figure 15. PLL Phase Noise Variation vs. fPD
LMX2594 tc_PhaseNoiseVsTempDelta.gif
fVCO = 8 GHz, Narrow Loop Bandwidth (<100 Hz)
Figure 17. CHANGE in 8-GHz VCO Phase Noise Over Temperature
LMX2594 tc_powervstemp.gif
Single-ended output with resistor pullup and OUTx_PWR = 50. Note that Near 13.3 to 14.3 GHz, output power can be impacted at hot temperature. See the Application Information section for more information.
Figure 19. Output Power vs Temperature
LMX2594 tc_dividernoise.gif
This noise adds to the scaled VCO Noise when the channel divider is used.
Figure 21. Additive VCO Divider Noise Floor
LMX2594 D003_SNAS696.gif
fOSC = 100 MHz Jitter = 52.6 fs (100 Hz - 100 MHz)
fPD = 200 MHz
Figure 4. Closed-Loop Phase Noise at 13 GHz
LMX2594 D005_SNAS696.gif
fOSC = 100 MHz Jitter = 46.9 fs (100 Hz - 100 MHz)
fPD = 200 MHz
Figure 6. Closed-Loop Phase Noise at 9 GHz
LMX2594 D011_SNAS696.gif
fOSC = 100 MHz Jitter = 44.1 fs (100 Hz - 100 MHz)
fPD = 200 MHz
Figure 8. Closed-Loop Phase Noise at 7.5 GHz
LMX2594 D010_SNAS696.gif
Figure 10. VCO Ramping 12-GHz to 12.125-GHz Calibration Free
LMX2594 D008_SNAS696.gif
CalTime = 33.6 µs = 5.8 µs (Core) + 14 µs (Fcal) + 13.8 µs (Ampcal)
fOSC = 200 MHz, fPD = 100 MHz, fVCO = 7.5 - 14 GHz, CHDIV = 2
Figure 12. VCO Unassisted Calibration
LMX2594 tc_pllnoisemetrics.gif
fVCO = 12 GHz fPD = 100 MHz
Figure 14. Calculation of PLL Noise Metrics
LMX2594 tc_PhaseNoiseVsTemp.gif
fVCO = 8 GHz, Narrow Loop Bandwidth (<100 Hz)
Figure 16. VCO Phase Noise Over Temperature
LMX2594 tc_powervspullup.gif
Single-Ended Output OUTx_PWR = 50
Figure 18. Output Power Across Frequency
LMX2594 D030_SNAS696.gif
Resistor pullup Normalized to maximum output power.
Figure 20. Output Power Normalized To Maximum Across OUTA_PWR With Resistor Pullup