JAJSDN8C March   2017  – April 2019 LMX2594

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reference Oscillator Input
      2. 8.3.2  Reference Path
        1. 8.3.2.1 OSCin Doubler (OSC_2X)
        2. 8.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 8.3.2.3 Programmable Multiplier (MULT)
        4. 8.3.2.4 Post-R Divider (PLL_R)
        5. 8.3.2.5 State Machine Clock
      3. 8.3.3  PLL Phase Detector and Charge Pump
      4. 8.3.4  N-Divider and Fractional Circuitry
      5. 8.3.5  MUXout Pin
        1. 8.3.5.1 Lock Detect
        2. 8.3.5.2 Readback
      6. 8.3.6  VCO (Voltage-Controlled Oscillator)
        1. 8.3.6.1 VCO Calibration
        2. 8.3.6.2 Determining the VCO Gain
      7. 8.3.7  Channel Divider
      8. 8.3.8  Output Buffer
      9. 8.3.9  Power-Down Modes
      10. 8.3.10 Phase Synchronization
        1. 8.3.10.1 General Concept
        2. 8.3.10.2 Categories of Applications for SYNC
        3. 8.3.10.3 Procedure for Using SYNC
        4. 8.3.10.4 SYNC Input Pin
      11. 8.3.11 Phase Adjust
      12. 8.3.12 Fine Adjustments for Phase Adjust and Phase SYNC
      13. 8.3.13 Ramping Function
        1. 8.3.13.1 Manual Pin Ramping
          1. 8.3.13.1.1 Manual Pin Ramping Example
        2. 8.3.13.2 Automatic Ramping
          1. 8.3.13.2.1 Automatic Ramping Example (Triangle Wave)
      14. 8.3.14 SYSREF
        1. 8.3.14.1 Programmable Fields
        2. 8.3.14.2 Input and Output Pin Formats
          1. 8.3.14.2.1 Input Format for SYNC and SysRefReq Pins
          2. 8.3.14.2.2 SYSREF Output Format
        3. 8.3.14.3 Examples
        4. 8.3.14.4 SYSREF Procedure
      15. 8.3.15 SysRefReq Pin
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Recommended Initial Power-Up Sequence
      2. 8.5.2 Recommended Sequence for Changing Frequencies
      3. 8.5.3 General Programming Requirements
    6. 8.6 Register Maps
      1. 8.6.1  General Registers R0, R1, & R7
        1. Table 24. Field Descriptions
      2. 8.6.2  Input Path Registers
        1. Table 25. Field Descriptions
      3. 8.6.3  Charge Pump Registers (R13, R14)
        1. Table 26. Field Descriptions
      4. 8.6.4  VCO Calibration Registers
        1. Table 27. Field Descriptions
      5. 8.6.5  N Divider, MASH, and Output Registers
        1. Table 28. Field Descriptions
      6. 8.6.6  SYNC and SysRefReq Input Pin Register
        1. Table 29. Field Descriptions
      7. 8.6.7  Lock Detect Registers
        1. Table 30. Field Descriptions
      8. 8.6.8  MASH_RESET
        1. Table 31. Field Descriptions
      9. 8.6.9  SysREF Registers
        1. Table 32. Field Descriptions
      10. 8.6.10 CHANNEL Divider Registers
        1. Table 33. Field Descriptions
      11. 8.6.11 Ramping and Calibration Fields
        1. Table 34. Field Descriptions
      12. 8.6.12 Ramping Registers
        1. 8.6.12.1 Ramp Limits
          1. Table 35. Field Descriptions
        2. 8.6.12.2 Ramping Triggers, Burst Mode, and RAMP0_RST
          1. Table 36. Field Descriptions
        3. 8.6.12.3 Ramping Configuration
          1. Table 37. Field Descriptions
      13. 8.6.13 Readback Registers
        1. Table 38. Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 OSCin Configuration
      2. 9.1.2 OSCin Slew Rate
      3. 9.1.3 RF Output Buffer Power Control
      4. 9.1.4 RF Output Buffer Pullup
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

8.6 Register Maps

Table 23. Full Register Map

R/W A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R0 0 0 0 0 0 0 0 0 RAMP
_EN		 VCO_PHASE_SYNC 1 0 0 1 OUT_MUTE FCAL_HPFD_ADJ FCAL_LPFD_ADJ 1 FCAL
_EN		 MUXOUT_LD_SEL RESET POWERDOWN
R1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 CAL_CLK_DIV
R2 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0
R3 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0
R4 0 0 0 0 0 1 0 0 ACAL_CMP_DLY 0 1 0 0 0 0 1 1
R5 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0
R6 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0
R7 0 0 0 0 0 1 1 1 0 OUT_FORCE 0 0 0 0 0 0 1 0 1 1 0 0 1 0
R8 0 0 0 0 1 0 0 0 0 VCO_DACISET_FORCE 1 0 VCO_CAPCTRL_FORCE 0 0 0 0 0 0 0 0 0 0 0
R9 0 0 0 0 1 0 0 1 0 0 0 OSC_2X 0 1 1 0 0 0 0 0 0 1 0 0
R10 0 0 0 0 1 0 1 0 0 0 0 1 MULT 1 0 1 1 0 0 0
R11 0 0 0 0 1 0 1 1 0 0 0 0 PLL_R 1 0 0 0
R12 0 0 0 0 1 1 0 0 0 1 0 1 PLL_R_PRE
R13 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R14 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 CPG 0 0 0 0
R15 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1
R16 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 VCO_DACISET
R17 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 VCO_DACISET_STRT
R18 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0
R19 0 0 0 1 0 0 1 1 0 0 1 0 0 1 1 1 VCO_CAPCTRL
R20 0 0 0 1 0 1 0 0 1 1 VCO_SEL VCO_SEL
_FORCE		 0 0 0 1 0 0 1 0 0 0
R21 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1
R22 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R23 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0
R24 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 0
R25 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 1
R26 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0
R27 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
R28 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0
R29 0 0 0 1 1 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0
R30 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0
R31 0 0 0 1 1 1 1 1 0 CHDIV
_DIV2		 0 0 0 0 1 1 1 1 1 0 1 1 0 0
R32 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 1
R33 0 0 1 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1
R34 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_N[18:16]
R35 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
R36 0 0 1 0 0 1 0 0 PLL_N
R37 0 0 1 0 0 1 0 1 MASH
_SEED
_EN		 0 PFD_DLY_SEL 0 0 0 0 0 1 0 0
R38 0 0 1 0 0 1 1 0 PLL_DEN[31:16]
R39 0 0 1 0 0 1 1 1 PLL_DEN[15:0]
R40 0 0 1 0 1 0 0 0 [31:16]
R41 0 0 1 0 1 0 0 1 [15:0]
R42 0 0 1 0 1 0 1 0 PLL_NUM[31:16]
R43 0 0 1 0 1 0 1 1 PLL_NUM[15:0]
R44 0 0 1 0 1 1 0 0 0 0 OUTA_PWR OUTB_PD OUTA_PD MASH_RESET_N 0 0 MASH_ORDER
R45 0 0 1 0 1 1 0 1 1 1 0 OUTA_MUX OUT_ISET 0 1 1 OUTB_PWR
R46 0 0 1 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 OUTB_MUX
R47 0 0 1 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
R48 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
R49 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0
R50 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R51 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
R52 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0
R53 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R54 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R55 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R56 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R57 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
R58 0 0 1 1 1 0 1 0 INPIN_IGNORE INPIN_HYST INPIN_LVL INPIN_FMT 0 0 0 0 0 0 0 0 1
R59 0 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LD_TYPE
R60 0 0 1 1 1 1 0 0 LD_DLY
R61 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0
R62 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0
R63 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R64 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0
R65 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R66 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0
R67 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R68 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0
R69 0 1 0 0 0 1 0 1 MASH_RST_COUNT[31:16]
R70 0 1 0 0 0 1 1 0 MASH_RST_COUNT[15:0]
R71 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 SYSREF_DIV_PRE SYSREF_PULSE SYSREF_EN SYSREF_REPEAT 0 1
R72 0 1 0 0 1 0 0 0 0 0 0 0 0 SYSREF_DIV
R73 0 1 0 0 1 0 0 1 0 0 0 0 JESD_DAC2_CTRL JESD_DAC1_CTRL
R74 0 1 0 0 1 0 1 0 SYSREF_PULSE_CNT JESD_DAC4_CTRL JESD_DAC3_CTRL
R75 0 1 0 0 1 0 1 1 0 0 0 0 1 CHDIV 0 0 0 0 0 0
R76 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
R77 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R78 0 1 0 0 1 1 1 0 0 0 0 0 RAMP_THRESH[32] 0 QUICK_RECAL_EN VCO_CAPCTRL_STRT 1
R79 0 1 0 0 1 1 1 1 RAMP_THRESH[31:16]
R80 0 1 0 1 0 0 0 0 RAMP_THRESH[15:0]
R81 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMP_LIMIT_HIGH[32]
R82 0 1 0 1 0 0 1 0 RAMP_LIMIT_HIGH[31:16]
R83 0 1 0 1 0 0 1 1 RAMP_LIMIT_HIGH[15:0]
R84 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMP_LIMIT_LOW[32]
R85 0 1 0 1 0 1 0 1 RAMP_LIMIT_LOW[31:16]
R86 0 1 0 1 0 1 1 0 RAMP_LIMIT_LOW[15:0]
R87 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R88 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R89 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R90 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R91 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R92 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R93 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R94 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R95 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R96 0 1 1 0 0 0 0 0 RAMP_BURST_EN RAMP_BURST_COUNT 0 0
R97 0 1 1 0 0 0 0 1 RAMP0_RST 0 0 0 1 RAMP_TRIGB RAMP_TRIGA 0 RAMP_BURST_TRIG
R98 0 1 1 0 0 0 1 0 RAMP0_INC[29:16] 0 RAMP0_DLY
R99 0 1 1 0 0 0 1 1 RAMP0_INC[15:0]
R100 0 1 1 0 0 1 0 0 RAMP0_LEN
R101 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 RAMP1
_DLY		 RAMP1
_RST		 RAMP0
_NEXT		 0 0 RAMP0
_NEXT
_TRIG
R102 0 1 1 0 0 1 1 0 0 0 RAMP1_INC[29:16]
R103 0 1 1 0 0 1 1 1 RAMP1_INC[15:0]
R104 0 1 1 0 1 0 0 0 RAMP1_LEN
R105 0 1 1 0 1 0 0 1 RAMP_DLY_CNT RAMP_MANUAL RAMP1_NEXT 0 0 RAMP1_NEXT_TRIG
R106 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 RAMP_TRIG_CAL 0 RAMP_SCALE_COUNT
R107 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R108 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R109 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R110 0 1 1 0 1 1 1 0 0 0 0 0 0 rb_LD_VTUNE 0 rb_VCO_SEL 0 0 0 0 0
R111 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 rb_VCO_CAPCTRL
R112 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 rb_VCO_DACISET