JAJSDR4C August   2017  – May 2019 INA1650-Q1 , INA1651-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     簡略化された内部回路図
  3. 3 概要
    1.     CMRRヒストグラム(5746チャネル)
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions: INA1650-Q1
    2.     Pin Functions: INA1651-Q1
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics:
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Audio Signal Path
      2. 7.3.2 Supply Divider
      3. 7.3.3 EMI Rejection
      4. 7.3.4 Electrical Overstress
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Single-Supply Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Common-Mode Range
      2. 8.1.2 Common-Mode Input Impedance
      3. 8.1.3 Start-Up Time in Single-Supply Applications
      4. 8.1.4 Input AC Coupling
      5. 8.1.5 Supply Divider Capacitive Loading
    2. 8.2 Typical Applications
      1. 8.2.1 Line Receiver for Differential Audio Signals in a Split-Supply System
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Two-Channel Microphone Input for Automotive Infotainment Systems
      3. 8.2.3 TRS Audio Interface in Single-Supply Applications
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 TINA-TI(無料のダウンロード・ソフトウェア)
        2. 11.1.1.2 TI Precision Designs
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

10.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

  • Connect low-ESR, 1-µF and 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close as possible to the device. Connecting bypass capacitors only from V+ to ground is acceptable in single-supply applications. Noise can propagate into analog circuitry through the power pins of this device. The bypass capacitors reduce the coupled noise by providing low-impedance pathways to ground.
  • Connect the device REF pins to a low-impedance, low-noise, system reference point (such as an analog ground or the VMID(OUT) pin) with the shortest trace possible.
  • Place the external components as close to the device as possible, as shown in Figure 62 and Figure 63.
  • Use ground pours and planes to shield input signal traces and minimize additional noise introduced into the signal path.
  • Keep the length of input traces equal and as short as possible. Route the input traces as a differential pair with as minimal spacing between them as possible.