JAJSDR6C August   2017  – February 2022 TIC12400-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Mode Selection
        3. 8.3.8.3 Input Enable Selection
        4. 8.3.8.4 Thresholds Adjustment
        5. 8.3.8.5 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable or Disable and Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check and Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
        1. 8.4.2.1 Standard Polling
        2. 8.4.2.2 Matrix polling
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
        3. 8.4.3.3 VS Measurement
        4. 8.4.3.4 Wetting Current Diagnostic
        5. 8.4.3.5 ADC Self-Diagnostic
    5. 8.5 Programming
      1. 8.5.1 SPI Communication Interface Buses
        1. 8.5.1.1 Chip Select ( CS)
        2. 8.5.1.2 System Clock (SCLK)
        3. 8.5.1.3 Slave In (SI)
        4. 8.5.1.4 Slave Out (SO)
      2. 8.5.2 SPI Sequence
        1. 8.5.2.1 Read Operation
        2. 8.5.2.2 Write Operation
        3. 8.5.2.3 Status Flag
    6. 8.6 Register Maps
    7. 8.7 Programming Guidelines
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Using TIC12400-Q1 in a 12 V Automotive System
    3. 9.3 Resistor-coded Switches Detection in Automotive Body Control Module
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.3.8.4 Thresholds Adjustment

When an input is configured as comparator input mode, the threshold level for interrupt generation can be programmed by setting the THRES_COMP register. The threshold level settings can be set for each individual input groups and each group consists of 4 inputs. Four threshold levels are available: 2 V, 2.7 V, 3 V, and 4 V.

When an input is configured as ADC input mode the threshold level for interrupt generation can be configured from 0 to 1023 different levels by setting the THRES_CFG1 to THRES_CFG2 registers. One threshold level can be programmed individually for each of the inputs from IN0 to IN11. Additionally, one common threshold, shared between inputs IN0 to IN11, can be programmed by configuring the THRES_COM bits in register MATRIX. The common threshold acts independently from the threshold THRES0 to THRES7. Inputs IN12 to IN17 use 2 preset threshold levels (THRES2A and THRES2B). Inputs 18 to 22 use 3 preset threshold levels (THRES3A, THRES3B, and THRES3C). Input 23 uses 5 preset threshold levels (THRES3A, THRES3B, THRES3C, THRES8, and THRES9).

When multiple threshold settings are used for ADC inputs, the thresholds levels need to be configured properly. Use the rules below (see Table 8-2) when setting up the threshold levels:

Table 8-2 Proper Threshold Configuration for ADC Inputs
INPUTPROPER THRESHOLD CONFIGURATION
IN12 to IN17THRES2B ≥ THRES2A
IN18 to IN22THRES3C ≥ THRES3B ≥ THRES3A
IN23THRES9 ≥ THRES8 ≥ THRES3C ≥ THRES3B ≥ THRES3A

Remember to use caution when setting up the threshold for switches that are connected externally to the battery as there is a finite voltage drop (as high as VCSI_DROP_OPEN for 10 mA and 15 mA settings) across the current sinks. Therefore, even for an open switch, the voltage on the INx pin can be as high as VCSI_DROP_OPEN and the detection threshold shall be configured above it. It shall also be noted that a lower wetting current sink setting may not be strong enough to pull the INx pin close to ground in the presence of a leaky open external switch, as illustrated in the diagram below (see Figure 8-3). In this example, the external switch, although in the open state, has large leakage current and can be modelled as an equivalent resistor (RDIRT) of 5 kΩ. The 2 mA current sink is only able to pull the INx pin voltage down to 4 V, even if the switch is in the open state.

GUID-19968CA4-DE4C-4EB3-A586-AB37CEE01862-low.gifFigure 8-3 Example Showing the Calculation of the INx Pin Voltage for A Leaky Battery-Connected Switch

It is possible to configure an input to ADC input mode, instead of comparator input mode, to monitor single-threshold digital switches. The following programming procedure is recommended under such configuration:

Table 8-3 Recommended Threshold Configuration When Using an ADC Input to Monitor Digital Switches
INPUTRECOMMENDED THRESHOLD CONFIGURATION
IN0 to IN11Configure the desired threshold to one of the settings from THRES0 to THRES7 and map it accordingly
IN12 to IN17
  • Configure the desired threshold to THRES2B
  • Set THRES2A to the same code as THRES2B
  • Disable interrupt generation for THRES2A by configuring the INT_EN_CFG1 or INT_EN_CFG2 register.
IN18 to IN22
  • Configure the desired threshold to THRES3C
  • Set THRES3A and THRES3B to the same code as THRES3C.
  • Disable interrupt generation for THRES3A and THRES3B by configuring the INT_EN_CFG3 or INT_EN_CFG4 register.
IN23
  • Configure the desired threshold to THRES9
  • Set THRES3A, THRES3B, THRES3C, and THRES8 to the same code as THRES9.
  • Disable interrupt generation for THRES3A, THRES3B, THRES3C, and THRES8 by configuring the INT_EN_CFG4 register.