JAJSDR6C August   2017  – February 2022 TIC12400-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Mode Selection
        3. 8.3.8.3 Input Enable Selection
        4. 8.3.8.4 Thresholds Adjustment
        5. 8.3.8.5 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable or Disable and Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check and Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
        1. 8.4.2.1 Standard Polling
        2. 8.4.2.2 Matrix polling
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
        3. 8.4.3.3 VS Measurement
        4. 8.4.3.4 Wetting Current Diagnostic
        5. 8.4.3.5 ADC Self-Diagnostic
    5. 8.5 Programming
      1. 8.5.1 SPI Communication Interface Buses
        1. 8.5.1.1 Chip Select ( CS)
        2. 8.5.1.2 System Clock (SCLK)
        3. 8.5.1.3 Slave In (SI)
        4. 8.5.1.4 Slave Out (SO)
      2. 8.5.2 SPI Sequence
        1. 8.5.2.1 Read Operation
        2. 8.5.2.2 Write Operation
        3. 8.5.2.3 Status Flag
    6. 8.6 Register Maps
    7. 8.7 Programming Guidelines
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Using TIC12400-Q1 in a 12 V Automotive System
    3. 9.3 Resistor-coded Switches Detection in Automotive Body Control Module
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.4.3.3 VS Measurement

When the TIC12400-Q1 is used to monitor resistor-coded switches, the VS supply voltage level becomes critical. If VS is not sufficiently high, the device might not have enough headroom to produce accurate wetting currents. This could impact the accuracy of the switch status monitoring. It is imperative for the microcontroller to have knowledge of the VS voltage on a constant basis in such a case.

Measurement of VS voltage is a feature in TIC12400-Q1 that can be enabled by setting the VS_MEAS_EN bit in register CONFIG to logic 1. If enabled, at the end of every detection and polling cycle, the voltage on the VS pin is sampled and converted by the ADC to a digital value. The conversion takes one extra tADC, and the converted value is recorded in the ANA_STAT12 register.

The VS measurement supports two different VS voltage ranges that can be configured by the VS_RATIO bit in the CONFIG register. By default (VS_RATIO= logic 0), the supported VS voltage range is from 4.5 V to 9 V, and VS voltage in excess of 9 V results in a saturated ADC raw code of 1023. This setting provides better measurement resolution at lower VS voltages. When VS_RATIO bit is set to logic 1, the supported VS voltage range is widened to 4.5 V to 30 V, and VS voltage in excess of 30 V results in a saturated ADC raw code of 1023. This setting allows wider measurement range but more coarse measurement resolution. It is important to adjust the detection thresholds accordingly depending on the VS voltage range configured.

Four different measurement thresholds can be programmed by the TIC12400-Q1: VS0_THRES2A/B and VS1_THRES2A/B. The value of these thresholds can be programmed by configuring registers THRES_CFG0 to THRES_CFG3 and the mapping can be programmed by configuring registers THRESMAP_VS0_THRES2A/B and THRESMAP_VS1_THRES2A/B bits in the register THRESMAP_CFG2. When setting the thresholds follow the rules in Table 8-9 below.

Table 8-9 Proper Threshold Configuration for VS Measurements
VS THRESHOLDPROPER THRESHOLD CONFIGURATION
VS0VS0_THRES2B ≥ VS0_THRES2A
VS1VS1_THRES2B ≥ VS1_THRES2A

After the VS measurement is enabled for the first time, the VS measurement interrupt is always generated ( INT pin is asserted low, and the VS0 or VS1 bit in the INT_STAT register is flagged to logic 1) at the end of the first polling cycle to notify the microcontroller the initial VS measurement result is ready to be retrieved. The VS0_STAT and VS1_STAT bits from register IN_STAT_MISC indicate the status of the VS voltage with respect to the thresholds, and the ANA_STAT12 register stores the converted digital value of the VS voltage. The SPI status flag VS_TH is also asserted to logic 1 during SPI communications. Note the status detected in the first polling cycle becomes the baseline value of comparison for subsequent VS measurements and the interrupt will be generated only if threshold crossing is detected.

Similar to regular inputs, the interrupt generation conditions can be programmed by setting the VS_TH0_EN and VS_TH1_EN bits in the INT_EN_CFG4 register to the following settings:

  1. Rising edge: an interrupt is generated if the current VS measurement is above the corresponding threshold and the previous measurement was below.
  2. Falling edge: an interrupt is generated if the current VS measurement is below the corresponding threshold and the previous measurement was above.
  3. Both edges: changes of the VS measurement status in either direction results in an interrupt generation.

Interrupt generation can also be disabled by setting VS_TH0_EN or VS_TH1_EN to logic 0 in register INT_EN_CFG4. Once disabled, VS voltage crossing does not flag the VS0 or VS1 bit in INT_STAT register and does not assert INT pin low. To only mask the INT pin from assertion (while keeping INT_STAT register updated), configure the VS1_EN and VS0_EN bits in register INT_EN_CFG0 to logic 0.

Note the VS measurement is only intended to be used as part of switch detection sequence to determine the validity of the switch detection states that are reported by the TIC12400-Q1. It is not intended to be used for standalone supply monitoring, such as monitoring cranking voltages, due to the potentially delayed response being part of the polling sequence. The VS measurement result is accurate for VS above 4.5 V.

By default, the VS voltage measurement is disabled upon device reset.