JAJSDX8E June   2017  – August 2018 ISO1211 , ISO1212

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション図
      2.      従来のソリューションと比較した、ISO121xデバイスによる基板の温度の低下
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics—DC Specification
    10. 7.10 Switching Characteristics—AC Specification
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Sinking Inputs
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Setting Current Limit and Voltage Thresholds
          2. 10.2.1.2.2 Thermal Considerations
          3. 10.2.1.2.3 Designing for 48-V Systems
          4. 10.2.1.2.4 Designing for Input Voltages Greater Than 60 V
          5. 10.2.1.2.5 Surge, ESD, and EFT Tests
          6. 10.2.1.2.6 Multiplexing the Interface to the Host Controller
          7. 10.2.1.2.7 Status LEDs
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Sourcing Inputs
      3. 10.2.3 Sourcing and Sinking Inputs (Bidirectional Inputs)
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

7.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATION UNIT
D-8 DBQ-16
CLR External clearance(1) Shortest terminal-to-terminal distance through air 4 3.7 mm
CPG External Creepage(1) Shortest terminal-to-terminal distance across the package surface 4 3.7 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) 10.5 10.5 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 > 600 V
Material Group According to IEC 60664-1 I I
Overvoltage category Rated mains voltage ≤ 150 VRMS I-IV I-IV
Rated mains voltage ≤ 300 VRMS I-III I-III
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 566 566 VPK
VIOWM Maximum working isolation voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test 400 400 VRMS
DC voltage 566 566 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification),
VTEST = VIOTM, t= 1 s (100% production)		 3600 3600 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065-1, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 5200 VPK (qualification)		 4000 4000 VPK
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 680 VPK, tm = 10 s		 < 5 < 5 pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.3 × VIORM = 736 VPK, tm = 10 s		 < 5 < 5
Method b1: At routine test (100% production) and preconditioning (type test),
Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.5 × VIORM = 849 VPK, tm = 10 s		 < 5 < 5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2 πft), f = 1 MHz 440 560 fF
RIO Insulation resistance, input to output(5) VIO = 500 V,  TA = 25°C > 1012 > 1012 Ω
VIO = 500 V,  100°C ≤ TA ≤ 125 °C > 1011 > 1011
VIO = 500 V at  TS = 150 °C > 109 > 109
Pollution degree 2 2
Climatic category 40/125/21 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 2500 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 3000 VRMS, t = 1 s (100% production)		 2500 2500 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device