4 Revision History
Changes from Revision C (October 2020) to Revision D (March 2023)
- 先頭ページにある消費電力の標準値の箇条書き項目を電気的特性の表に合わせて更新Go
- IDD_TOTAL typical value changed to 160 mAGo
- Changed I2C terminology to "Controller" and
"Target"Go
- Removed extra arrow from DPHY Receiver to Clock Gen blocks in
Functional Block DiagramGo
- Added description for non-continuous clock lane modeGo
- Added description for deserializer SENSOR_STS registersGo
- Updated script example for voltage monitoringGo
- Updated description for reading GPIO status when set as output and
added GPIO Configuration tableGo
- Added information for enabling Forward Channel GPIO using
FC_GPIO_ENGo
- Updated GPIO Output Control section description for enabling
register 0x0EGo
- Added typical latency to Forward Channel GPIO tableGo
- Updated Clocking Mode table with additional modes, frequency
clarifications, and CSI-2 bandwidth clarificationsGo
- Corrected effect of setting M value in register 0x06 Go
- Updated description to refer to "DVP_DT_MATCH_EN" in register 0x11. Go
- Changed 0x17[7:4] default value from 0x0 to 0x3Go
- Added max and min readings to Voltage Sensor Thresholds description
in Register 0x19 Go
- Updated SENSOR_V1_THRESH description to match SENSOR_V0_THRESH in
register 0x1AGo
- Changed "GPIO0 Sensor" to "Internal Temperature Sensor" in register
0x57Go
- Changed "FPD3_RX_ID" to "FPD3_TX_ID" in registers
0xF0-0xF5Go
- Changed PoC network impedance recommendation from 2 kΩ to 1
kΩGo
- Updated PoC descriptionGo
- Removed IL and RL values from Suggested Characteristics for
Single-Ended PCB Traces With Attached PoC Networks TableGo
- Changed FB1-FB3 requirement to DCR < 500 mΩ.Go
- Added note for setting watchdog timer for system
initializationGo
- Corrected PDB capacitor from 1-μF to 10-μFGo
Changes from Revision B (September 2018) to Revision C (October 2020)
- 「特長」の箇条書き項目に「機能安全対応」を追加。Go
Changes from Revision A (February 2018) to Revision B (September 2018)
- Updated GPIO pin descriptions. Go
- Replace CLK_IN with clock throughout document. Go
- Changed Supply voltage from 2.5V to 2.16VGo
- Changed asynchronous to non-synchronousGo
- Deleted "for synchronous mode"Go
- Added internal reference frequency in EC tableGo
- Added Internal AON Clock to Block Diagram.Go
- Changed mode to modes. Go
- Changed 130ns to 225ns.Go
- Changed latency to 1.5us and jitter to 0.7us. Go
- Changed CLK_IN Mode to Modes. Go
- Added DVP Mode Go
- Changed table formatting. Go
- Changed REFLCK to Back Channel Go
- Added Frequency for Synchronous Mode Go
- Changed naming convention from "asynchronous CLK_IN" to
"Non-Synchronous external CLK_IN" mode column dor CLKIN_DIV = 2Go
- Added Non-Synchronous Internal Clock Mode Go
- Changed the value from 24.2 - 25.5 MHz to 48.4 - 51 MHz Go
- Changed the value from 25 - 52 MHz to 24.2 to 25.5 MHz Go
- Added DVP External Clock.Go
- Added text "Deserializer Mode" to clarify mode RAW10 Go
- Added text "Deserializer Mode" to clarify mode RAW12 HF Go
- Added additional information to note. Go
- Added Added Footnote for Local Reference Source Go
- Changed CLK_IN to Clock.Go
- Added Non-Synchronous Internal Clocking Mode section. Go
- Changed the internal clock 25 MHz to 24.2 MHz Go
- Changed forward channel rate to1.936 Gbps instead of 2 Gbps Go
- Changed the average CSI-2 throughput value to 3.1 Gbps instead of
1.6 Gbps Go
- Added DVP Backwards Compatibility Mode section.Go
- Changed "asynchronous CLK_IN" to "Non-Synchronous external CLK_IN"Go
- Added sentence "CLK_OUT functionality is not..."Go
- Added Non-Synchronous Internal Clock Mode Go
- Deleted "with accuracy of 25 MHz ±10%.Go
- Changed clock to from 25 MHz ±10% to 26.25 MHz. Go
- Changed clock to from 25 MHz ±10% to 26.25 MHz. Go
- Updated registers map Go
- Added information for DVP mode to register 0x04. Go
- Added "operating with Non-Synchronous internal clock
or"Go
- Added "operating with Non-Synchronous internal clock
or"Go
- Changed the frequency value from 26 MHz to range value (24.2 MHz to 25.5 MHz) Go
- Added "set for 2 Gbps line rate" Go
- Changed the frequency value from 52 MHz to range value (48.4 MHz to 51 MHz) Go
- Added "set for 4 Gbps line rate" in register 0x05 Go
- Updated unit time and clock frequency. Go
- Added DVP information to register 0x10. Go
- Added DVP information to register 0x11. Go
- Deleted the value -25dB and added -20dB in typcial Go
- Changed –26.4+14.4f to log equation –12+8*log(f) Go
- Moved Return Loss, S11 MAX values to TYPGo
- Added Typical connection diagram for STP Go
- Changed the capacitance value from 33nF to 33nF – 100 nF. Go
- Changed the capacitance value from 15 nF to 15 nF – 47
nF.Go
- Changed the capacitance value from 33nF to 33nF – 100 nF. Go
Changes from Revision * (September 2017) to Revision A (December 2017)
- 「特長」の箇条書き項目に「機能安全対応」を追加。Go
- Changed RES1 pin description from "Leave OPEN" to "Do not connect" Go
- Added "Internal 1-MΩ pulldown" text to PDB pin descriptionGo
- Expanded MODE pin description Go
- Changed "Requires" to "Typically connected to" in the Power and Ground pin descriptions Go
- Changed "and should not be connected to an external supply" to "Do not connect to an external supply rail" in the Power and Ground pin descriptions Go
- Changed the CSI_ERR_COUNT (0x5C) text to CSI_ERR_CNT
(0x5C)Go
- Changed DS90UBUB954-Q1 to DS90UB954-Q1Go
- Changed the GPIO_INPUT_CTL text to GPIO_INPUT_CTRL in the GPIO Input Control and GPIO Output Control sectionsGo
- Changed CLK_IN lower limit with CLKIN_DIV =1 from 46 MHz to 25 MHz
and CLK_IN lower limit from 92 MHz to 50 MHz.Go
- Corrected typo in MODE description saying the number of modes is 3
to the correct value of 2Go
- Changed I2C START description to "A START occurs when SDA transitions Low while SCLK is High" Go
- Added sentence and table to clarify reserved registers Go
- Added registers tables for reserved registers 0x04, 0x0F-0x12, 0x16,
0x1F, 0x25-0x30, 0x34, 0x36, 0x38, 0x4A-0x4F, 0x5B, 0x65-0xAF, and
0xB3-0xEF.Go
- Changed bit 6 and bit 7 in the MODE_SEL register to
RESERVEDGo
- Changed the SENSE_VO_HI and SENSE_VO_LO registers to SENSE_V0_HI and
SENSE_V0_LO to match the title in Table 7-34
Go
- Changed the SENSE_V0_HI and SENSE_V0_LO bit
descriptionsGo
- Changed the SENSOR_V0_THRESH bit description Go
- Changed the SENSE_T_HI and SENSE_T_LO bit
descriptionsGo
- Combined the CSI_EN_HSRX register bits 6–0 into one
rowGo
- Combined the CSI_EN_LPRX register bits 6–0 into one
rowGo
- Combined the CSI_EN_RXTERM register bits 7–4 into one
rowGo
- Changed serializer to deserializer in TARGET_ID_ALIAS_x bit
descriptions Go
- Changed Target 0 to Target 1 in the TARGET_AUTO_ACK_1 bit
descriptionGo
- Changed Target 0 to Target 2 in the TARGET_AUTO_ACK_2 bit
descriptionGo
- Changed Target 0 to Target 3 in the TARGET_AUTO_ACK_3 bit
descriptionGo
- Changed Target 0 to Target 4 in the TARGET_AUTO_ACK_4 bit
descriptionGo
- Changed Target 0 to Target 5 in the TARGET_AUTO_ACK_5 bit
descriptionGo
- Changed Target 0 to Target 6 in the TARGET_AUTO_ACK_6 bit
descriptionGo
- Changed Target 0 to Target 7 in the TARGET_AUTO_ACK_7 bit
descriptionGo
- Changed CRC_ERR bit description in GENERAL_STATUS to match
CRC_ERR_CLR register name Go
- Changed the CNTRL_ERR_HSRQST_2 bit descriptionGo
- Changed Typical Applications Coaxial Diagram
captionGo
- Added PIN(S) column to Table 8-3
Go
- Changed large bulk capacitor typical range lower limit from 50 µF to
47 µF, removed mentions of dedicated power plane and tantalum capacitors, and
changed recommended power rating for capacitors in layout guidelines Go
- Changed recommended CSI-2 guidelines on matching trace lengths and routing to help trace impedanceGo
- Changed routing guidelines for the DOUT+ and DOUT– pins Go
- Added new links to the Related Documentation
sectionGo