JAJSDZ9 October   2017 ADS54J64

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  AC Performance
    7. 7.7  Digital Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Typical Characteristics: DDC Bypass Mode
    10. 7.10 Typical Characteristics: Mode 2
    11. 7.11 Typical Characteristics: Mode 0
    12. 7.12 Typical Characteristics: Dual ADC Mode
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 Recommended Input Circuit
      3. 8.3.3 Clock Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Digital Functions
        1. 8.4.1.1  Numerically Controlled Oscillators (NCOs) and Mixers
        2. 8.4.1.2  Decimation Filter
          1. 8.4.1.2.1 Stage-1 Filter
          2. 8.4.1.2.2 Stage-2 Filter
        3. 8.4.1.3  Mode 0: Decimate-by-4 With IQ Outputs and fS / 4 Mixer
        4. 8.4.1.4  Mode 1: Decimate-by-4 With IQ Outputs and 16-Bit NCO
        5. 8.4.1.5  Mode 2: Decimate-by-4 With Real Output
        6. 8.4.1.6  Mode 3: Decimate-by-2 Real Output With Frequency Shift
        7. 8.4.1.7  Mode 4: Decimate-by-4 With Real Output
        8. 8.4.1.8  Mode 6: Decimate-by-4 With IQ Outputs for Up to 110 MHz of IQ Bandwidth
        9. 8.4.1.9  Mode 7: Decimate-by-4 With Real Output and Zero Stuffing
        10. 8.4.1.10 Mode 8: DDC Bypass Mode
        11. 8.4.1.11 Averaging Mode
        12. 8.4.1.12 Overrange Indication
    5. 8.5 Programming
      1. 8.5.1 JESD204B Interface
      2. 8.5.2 JESD204B Initial Lane Alignment (ILA)
      3. 8.5.3 JESD204B Frame Assembly
      4. 8.5.4 JESD Output Switch
        1. 8.5.4.1 SerDes Transmitter Interface
        2. 8.5.4.2 SYNCb Interface
        3. 8.5.4.3 Eye Diagram
      5. 8.5.5 Device Configuration
        1. 8.5.5.1 Details of the Serial Interface
          1. 8.5.5.1.1 Register Initialization
        2. 8.5.5.2 Serial Register Write
        3. 8.5.5.3 Serial Read
    6. 8.6 Register Maps
      1. 8.6.1 Register Map
        1. 8.6.1.1 Register Description
          1. 8.6.1.1.1 GLOBAL Page Register Description
            1. 8.6.1.1.1.1 Register 00h (address = 00h) [reset = 0h], GLOBAL Page
              1. Table 9. Register 00h Field Descriptions
            2. 8.6.1.1.1.2 Register 04h (address = 04h) [reset = 0h], GLOBAL Page
              1. Table 10. Register 04h Field Descriptions
            3. 8.6.1.1.1.3 Register 11h (address = 11h) [reset = 0h], GLOBAL Page
              1. Table 11. Register 11h Field Descriptions
            4. 8.6.1.1.1.4 Register 12h (address = 12h) [reset = 0h], GLOBAL Page
              1. Table 12. Register 12h Field Descriptions
            5. 8.6.1.1.1.5 Register 13h (address = 13h) [reset = 0h], GLOBAL Page
              1. Table 13. Register 13h Field Descriptions
          2. 8.6.1.1.2 DIGTOP Page Register Description
            1. 8.6.1.1.2.1  Register 64h (address = 64h) [reset = 0h], DIGTOP Page
              1. Table 14. Register 64h Field Descriptions
            2. 8.6.1.1.2.2  Register 8Dh (address = 8Dh) [reset = 0h], DIGTOP Page
              1. Table 15. Register 8Dh Field Descriptions
            3. 8.6.1.1.2.3  Register 8Eh (address = 8Eh) [reset = 0h], DIGTOP Page
              1. Table 16. Register 8Eh Field Descriptions
            4. 8.6.1.1.2.4  Register 8Fh (address = 8Fh) [reset = 0h], DIGTOP Page
              1. Table 17. Register 8Fh Field Descriptions
            5. 8.6.1.1.2.5  Register 90h (address = 90h) [reset = 0h], DIGTOP Page
              1. Table 18. Register 90h Field Descriptions
            6. 8.6.1.1.2.6  Register 91h (address = 91h) [reset = 0h], DIGTOP Page
              1. Table 19. Register 91h Field Descriptions
            7. 8.6.1.1.2.7  Register A5h (address = A5h) [reset = 0h], DIGTOP Page
              1. Table 20. Register A5h Field Descriptions
            8. 8.6.1.1.2.8  Register A6h (address = A6h) [reset = 0h], DIGTOP Page
              1. Table 21. Register A6h Field Descriptions
            9. 8.6.1.1.2.9  Register ABh (address = ABh) [reset = 0h], DIGTOP Page
              1. Table 22. Register ABh Field Descriptions
            10. 8.6.1.1.2.10 Register ACh (address = ACh) [reset = 0h], DIGTOP Page
              1. Table 23. Register ACh Field Descriptions
            11. 8.6.1.1.2.11 Register ADh (address = ADh) [reset = 0h], DIGTOP Page
              1. Table 24. Register ADh Field Descriptions
            12. 8.6.1.1.2.12 Register AEh (address = AEh) [reset = 0h], DIGTOP Page
              1. Table 25. Register AEh Field Descriptions
            13. 8.6.1.1.2.13 Register B7h (address = B7h) [reset = 0h], DIGTOP Page
              1. Table 26. Register B7h Field Descriptions
            14. 8.6.1.1.2.14 Register 8Ch (address = 8Ch) [reset = 0h], DIGTOP Page
              1. Table 27. Register 8Ch Field Descriptions
          3. 8.6.1.1.3 ANALOG Page Register Description
            1. 8.6.1.1.3.1  Register 6Ah (address = 6Ah) [reset = 0h], ANALOG Page
              1. Table 28. Register 6Ah Field Descriptions
            2. 8.6.1.1.3.2  Register 6Fh (address = 6Fh) [reset = 0h], ANALOG Page
              1. Table 29. Register 6Fh Field Descriptions
            3. 8.6.1.1.3.3  Register 71h (address = 71h) [reset = 0h], ANALOG Page
              1. Table 30. Register 71h Field Descriptions
            4. 8.6.1.1.3.4  Register 72h (address = 72h) [reset = 0h], ANALOG Page
              1. Table 31. Register 72h Field Descriptions
            5. 8.6.1.1.3.5  Register 93h (address = 93h) [reset = 0h], ANALOG Page
              1. Table 32. Register 93h Field Descriptions
            6. 8.6.1.1.3.6  Register 94h (address = 94h) [reset = 0h], ANALOG Page
              1. Table 33. Register 94h Field Descriptions
            7. 8.6.1.1.3.7  Register 9Bh (address = 9Bh) [reset = 0h], ANALOG Page
              1. Table 34. Register 9Bh Field Descriptions
            8. 8.6.1.1.3.8  Register 9Dh (address = 9Dh) [reset = 0h], ANALOG Page
              1. Table 35. Register 9Dh Field Descriptions
            9. 8.6.1.1.3.9  Register 9Eh (address = 9Eh) [reset = 0h], ANALOG Page
              1. Table 36. Register 9Eh Field Descriptions
            10. 8.6.1.1.3.10 Register 9Fh (address = 9Fh) [reset = 0h], ANALOG Page
              1. Table 37. Register 9Fh Field Descriptions
            11. 8.6.1.1.3.11 Register AFh (address = AFh) [reset = 0h], ANALOG Page
              1. Table 38. Register AFh Field Descriptions
          4. 8.6.1.1.4 SERDES_XX Page Register Description
            1. 8.6.1.1.4.1  Register 20h (address = 20h) [reset = 0h], SERDES_XX Page
              1. Table 39. Register 20h Field Descriptions
            2. 8.6.1.1.4.2  Register 21h (address = 21h) [reset = 0h], SERDES_XX Page
              1. Table 40. Register 21h Field Descriptions
            3. 8.6.1.1.4.3  Register 22h (address = 22h) [reset = 0h], SERDES_XX Page
              1. Table 41. Register 22h Field Descriptions
            4. 8.6.1.1.4.4  Register 23h (address = 23h) [reset = 0h], SERDES_XX Page
              1. Table 42. Register 23h Field Descriptions
            5. 8.6.1.1.4.5  Register 25h (address = 25h) [reset = 0h], SERDES_XX Page
              1. Table 43. Register 25h Field Descriptions
            6. 8.6.1.1.4.6  Register 26h (address = 26h) [reset = 0h], SERDES_XX Page
              1. Table 44. Register 26h Field Descriptions
            7. 8.6.1.1.4.7  Register 28h (address = 28h) [reset = 0h], SERDES_XX Page
              1. Table 45. Register 28h Field Descriptions
            8. 8.6.1.1.4.8  Register 2Dh (address = 2Dh) [reset = 0h], SERDES_XX Page
              1. Table 46. Register 2Dh Field Descriptions
            9. 8.6.1.1.4.9  Register 36h (address = 36h) [reset = 0h], SERDES_XX Page
              1. Table 47. Register 36h Field Descriptions
            10. 8.6.1.1.4.10 Register 41h (address = 41h) [reset = 0h], SERDES_XX Page
              1. Table 48. Register 41h Field Descriptions
            11. 8.6.1.1.4.11 Register 42h (address = 42h) [reset = 0h], SERDES_XX Page
              1. Table 49. Register 42h Field Descriptions
          5. 8.6.1.1.5 CHX Page Register Description
            1. 8.6.1.1.5.1 Register 26h (address = 26h) [reset = 0h], CHX Page
              1. Table 50. Register 26h Field Descriptions
            2. 8.6.1.1.5.2 Register 27h (address = 27h) [reset = 0h], CHX Page
              1. Table 51. Register 27h Field Descriptions
            3. 8.6.1.1.5.3 Register 2Dh (address = 2Dh) [reset = 0h], CHX Page
              1. Table 52. Register 2Dh Field Descriptions
            4. 8.6.1.1.5.4 Register 78h (address = 78h) [reset = 0h], CHX Page
              1. Table 53. Register 78h Field Descriptions
            5. 8.6.1.1.5.5 Register 7Ah (address = 7Ah) [reset = 0h], CHX Page
              1. Table 54. Register 7Ah Field Descriptions
            6. 8.6.1.1.5.6 Register 7Bh (address = 7Bh) [reset = 0h], CHX Page
              1. Table 55. Register 7Bh Field Descriptions
            7. 8.6.1.1.5.7 Register 7Eh (address = 7Eh) [reset = 3h], CHX Page
              1. Table 56. Register 7Eh Field Descriptions
          6. 8.6.1.1.6 ADCXX Page Register Description
            1. 8.6.1.1.6.1 Register 07h (address = 07h) [reset = FFh], ADCXX Page
              1. Table 57. Register 07h Field Descriptions
            2. 8.6.1.1.6.2 Register 08h (address = 08h) [reset = 0h], ADCXX Page
              1. Table 58. Register 08h Field Descriptions
            3. 8.6.1.1.6.3 Register D5h (address = D5h) [reset = 0h], ADCXX Page
              1. Table 59. Register D5h Field Descriptions
            4. 8.6.1.1.6.4 Register 2Ah (address = 2Ah) [reset = 0h], ADCXX Page
              1. Table 60. Register 2Ah Field Descriptions
            5. 8.6.1.1.6.5 Register CFh (address = CFh) [reset = 0h], ADCXX Page
              1. Table 61. Register CFh Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 Frequency Planning
      4. 9.1.4 SNR and Clock Jitter
      5. 9.1.5 ADC Test Pattern
        1. 9.1.5.1 ADC Section
        2. 9.1.5.2 Transport Layer Pattern
        3. 9.1.5.3 Link Layer Pattern
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

9.1.3 Frequency Planning

The ADS54J64 uses an architecture where the ADCs are 2x interleaved followed by a digital decimation by 2. The 2x interleaved and decimation architecture comes with a unique advantage of improved linearity resulting from frequency planning. Frequency planning refers to choosing the clock frequency and signal band appropriately such that the harmonic distortion components, resulting from the analog front-end (LNA, PGA), can be made to fall outside the decimation filter pass band. In absence of the 2x interleave and decimation architecture, these components alias back in band and limit the performance of the signal chain. For example, for fCLK = 983.04 MHz and fIN = 184.32 MHz:

Second-order harmonic distortion (HD2) = 2 × 184.32 = 368.64 MHz

Pass band of the 2x decimation filter = 0 MHz to 245.76 MHz (0 to fCLK / 4)

The second-order harmonic performance improves by the stop-band attenuation of the filter (approximately 40 dBc) because the second-order harmonic frequency is outside the pass band of the decimation filter.

Figure 131 shows the harmonic components (HD2–HD5) that fall in the decimation pass band for the input clock rate (fCLK) of the 983.04-MHz and 100-MHz signal band around the center frequency of 184.32 MHz.

ADS54J64 D046_SBAS807.gif

NOTE:

fCLK = 983.04 MHz, signal band = 134.32 MHz to 234.32 MHz.
Figure 131. In-Band Harmonics for a Frequency Planned System

As shown in Figure 131, both HD2 and HD3 are completely out of band. HD4 and HD5 fall in the decimation pass band for some frequencies of the input signal band.

Through proper frequency planning, the specifications of the ADC antialias filter can be relaxed.