JAJSDZ9 データシート

7.8 Timing Characteristics

typical values are at T_A = 25°C, full temperature range is from T_MIN = –40°C to T_MAX = +100°C, input clock frequency = 1 GHz, 50% clock duty cycle, output sample rate = 500 MSPS, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-dBFS differential input, and f_IN = 190 MHz (unless otherwise noted)

			MIN	TYP	MAX	UNITS
SAMPLE TIMING CHARACTERISTICS
	Aperture delay		0.55		0.92	ns
	Aperture delay matching between two channels on the same device			±100		ps
	Aperture delay matching between two devices at the same temperature and supply voltage			±100		ps
	Aperture jitter			100		f_S rms
	Wake-up time	Global power-down		10		ms
	Wake-up time	Pin power-down (fast power-down)		5		µs
	Data latency: ADC sample to digital output	DDC bypass mode		116		Input clock cycles
	Data latency: ADC sample to digital output	DDC mode 0		204		Input clock cycles
t_{SU_SYSREF}	Setup time for SYSREF, referenced to input clock rising edge		350		900	ps
t_{H_SYSREF}	Hold time for SYSREF, referenced to input clock rising edge		100			ps
JESD OUTPUT INTERFACE TIMING CHARACTERISTICS
	Unit interval		100			ps
	Serial output data rate				10	Gbps
	Total jitter for BER of 1E-15 and lane rate = 10 Gbps			24		ps
	Random jitter for BER of 1E-15 and lane rate = 10 Gbps			0.95		ps rms
	Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps			8.8		ps, pk-pk
t_R, t_F	Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps			35		ps

Figure 1. Latency Timing Diagram in DDC Bypass Mode