JAJSDZ9 October 2017 ADS54J64
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTRL_K | CTRL_SER_ MODE |
0 | TRANS_TEST_EN | 0 | LANE_ALIGN | FRAME_ALIGN | TX_ILA_DIS |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CTRL_K | R/W | 0h | This bit is the enable bit for programming the number of frames per multi-frame. 0 : Five frames per multi-frame (default) 1 : Frames per multi-frame can be programmed using register 26h |
6 | CTRL_SER_MODE | R/W | 0h | This bit allows the SERDES_MODE setting in register 21h (bits 1-0) to be changed. 0 : Disabled 1 : Enables SERDES_MODE setting |
5 | 0 | R/W | 0h | Must read or write 0 |
4 | TRANS_TEST_EN | R/W | 0h | This bit generates the long transport layer test pattern mode, as per section 5.1.6.3 of the JESD204B specification. 0 : Test mode is disabled 1 : Test mode is enabled |
3 | 0 | R/W | 0h | Must read or write 0 |
2 | LANE_ALIGN | R/W | 0h | This bit inserts the lane-alignment character (K28.3) for the receiver to align to the lane boundary, as per section 5.3.3.5 of the JESD204B specification. 0 : Normal operation 1 : Inserts lane-alignment characters |
1 | FRAME_ALIGN | R/W | 0h | This bit inserts the frame-alignment character (K28.7) for the receiver to align to the lane boundary, as per section 5.3.3.5 of the JESD204B specification. 0 : Normal operation 1 : Inserts frame-alignment characters |
0 | TX_ILA_DIS | R/W | 0h | This bit disables sending the initial link alignment (ILA) sequence when SYNC is deasserted. 0 = Normal operation 1 = Disables ILA |