JAJSDZ9 October 2017 ADS54J64
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LINK_LAYER_TESTMODE_SEL | RPAT_SET_DISP | LMFC_MASK_RESET | 0 | 0 | 0 | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | LINK_LAYER_TESTMODE_SEL | R/W | 0h | These bits generate a pattern as per section 5.3.3.8.2 of the JESD204B document. 0 : Normal ADC data 1 : D21.5 (high-frequency jitter pattern) 2 : K28.5 (mixed-frequency jitter pattern) 3 : Repeat the initial lane alignment (generates a K28.5 character and continuously repeats lane alignment sequences) 4 : 12-octet RPAT jitter pattern 6 : PRBS pattern (PRBS7, 15, 23, 31); use PRBS_MODE (register 36h, bits 7-6) to select the PRBS pattern |
4 | RPAT_SET_DISP | R/W | 0h | This bit changes the running disparity in the modified RPAT pattern test mode (only when the link layer test mode = 100). 0 : Normal operation 1 : Changes disparity |
3 | LMFC_MASK_RESET | R/W | 0h | 0 : Default 1 : Resets the LMFC mask |
2-0 | 0 | R/W | 0h | Must read or write 0 |