JAJSE12A October   2017  – October 2017 TPS92830-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Bias
        1. 8.3.1.1 Power-On-Reset (POR)
        2. 8.3.1.2 Current Reference (IREF)
        3. 8.3.1.3 Low-Current Fault Mode
      2. 8.3.2 Charge Pump
        1. 8.3.2.1 Charge Pump Architecture
      3. 8.3.3 Constant-Current Driving
        1. 8.3.3.1 High-Side Current Sense
        2. 8.3.3.2 High-Side Current Driving
        3. 8.3.3.3 Gate Overdrive Voltage Protection
        4. 8.3.3.4 High-Precision Current Regulation
        5. 8.3.3.5 Parallel MOSFET Driving
      4. 8.3.4 PWM Dimming
        1. 8.3.4.1 Supply Dimming
        2. 8.3.4.2 PWM Dimming by Input
        3. 8.3.4.3 Internal Precision PWM Generator
        4. 8.3.4.4 Full Duty-Cycle Switch
      5. 8.3.5 Analog Dimming
        1. 8.3.5.1 Analog Dimming Topology
        2. 8.3.5.2 Internal High-Precision Pullup Current Source
      6. 8.3.6 Output Current Derating
        1. 8.3.6.1 Output-Current Derating Topology
      7. 8.3.7 Diagnostics and Fault
        1. 8.3.7.1 LED Short-to-GND Detection
        2. 8.3.7.2 LED Short-to-GND Auto Retry
        3. 8.3.7.3 LED Open-Circuit Detection
        4. 8.3.7.4 LED Open-Circuit Auto Retry
        5. 8.3.7.5 Dropout-Mode Diagnostics
        6. 8.3.7.6 Overtemperature Protection
        7. 8.3.7.7 FAULT Bus Output With One-Fails–All-Fail
        8. 8.3.7.8 Fault Table
    4. 8.4 Device Functional Modes
      1. 8.4.1 Undervoltage Lockout, V(IN) < V(UVLO)
      2. 8.4.2 Normal Operation (V(IN) ≥ 4.5 V, V(IN) > V(LED) + 0.5 V)
      3. 8.4.3 Low-Voltage Dropout
      4. 8.4.4 Fault Mode (Fault Is Detected)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application for Automotive Exterior Lighting With One-Fails–All-Fail
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 High-Precision Dual-Brightness PWM Generation
        1. 9.2.2.1 Dual-Brightness Application
        2. 9.2.2.2 Design Requirements
        3. 9.2.2.3 Detailed Design Procedure
        4. 9.2.2.4 Application Curve
      3. 9.2.3 Driving High-Current LEDs With Parallel MOSFETs
        1. 9.2.3.1 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

6 Pin Configuration and Functions

PW Package
28-Pin TSSOP
Top View

Pin Functions

PINI/ODESCRIPTION
NAMENO.
CP1N 2 O Charge pump first-stage flying capacitor negative output, charge pump to provide gate-drive voltage for external MOSFET. Connect a 10-nF flying capacitor between CP1P and CP1N.
CP1P 1 O Charge pump first-stage flying capacitor positive output
CP2N 4 O Charge pump second-stage flying capacitor negative output. Connect a 10-nF flying capacitor between CP2P and CP2N.
CP2P 5 O Charge pump second-stage flying capacitor positive output
CPOUT 6 O Charge-pump output voltage. Connect a 150-nF storage capacitor between CPOUT and IN.
DERATE 9 I Voltage input for current derating. Connect to GND to disable the derate feature.
DIAGEN 8 I Input pin with comparator to enable diagnostics to avoid false open-fault diagnostics when the device works in low-dropout mode. Use a resistor divider to set a threshold according to the LED forward voltage.
FAULT 17 I/O Fault bus pin to support one-fails–all-fail feature. Float: one-fails–all-fail; strong pullup: only-fails-off
FD 13 I Full duty-cycle input, HIGH: 100% PWM; LOW: using external resistor-capacitor network to set PWM duty cycle
G1 26 O Channel 1 gate driver output, connect to CH 1 N-channel MOSFET gate
G2 23 O Channel 2 gate driver output, connect to CH 2 N-channel MOSFET gate
G3 20 O Channel 3 gate driver output, connect to CH 3 N-channel MOSFET gate
GND 3 — GND
ICTRL 14 I Analog dimming input, modulates the regulation voltage across the current-sense resistor. Apply a voltage source or connect a resistor between ICTRL and GND to set the analog dimming ratio.
IN 7 I Power supply for the device. LED current only flows from the external MOSFET to the LED.
ISN1 27 I Channel 1 current-sense negative input. Connect a current-sense resistor between ISP and ISN1 to set the CH 1 current.
ISN2 24 I Channel 2 current-sense negative input. Connect a current-sense resistor between ISP and ISN2 to set the CH 2 current.
ISN3 21 I Channel 3 current-sense negative input. Connect a current-sense resistor between ISP and ISN3 to set the CH 3 current.
IREF 15 O Internal current reference. Connect an 8-kΩ resistor between IREF and GND,
ISP 28 I Channel current-sense positive input. Kelvin-sense to LED sense-resistor positive node.
PWM1 10 I Channel 1 PWM input
PWM2 11 I Channel 2 PWM input
PWM3 12 I Channel 3 PWM input
PWMCHG 16 I/O On-chip PWM generator pin for external R-C. Connect a resistor and a capacitor between PWMCHG and GND to set the PWM duty cycle and frequency.
PWMOUT 18 O High-voltage PWM open-drain output. Connect a 10-kΩ resistor between IN and PWMOUT
SENSE1 25 I/O Channel 1 diagnostics pin. Connect to the CH 1 MOSFET source terminal
SENSE2 22 I/O Channel 2 diagnostics pin. Connect to the CH 2 MOSFET source terminal
SENSE3 19 I/O Channel 3 diagnostics pin. Connect to the CH 3 MOSFET source terminal