JAJSE13B October   2017  – July 2018 UCC21520-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety-Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Propagation Delay and Pulse Width Distortion
    2. 8.2 Rising and Falling Time
    3. 8.3 Input and Disable Response Time
    4. 8.4 Programable Dead Time
    5. 8.5 Power-up UVLO Delay to OUTPUT
    6. 8.6 CMTI Testing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in the UCC21520-Q1
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead Time (DT) Pin
        1. 9.4.2.1 Tying the DT Pin to VCC
        2. 9.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing INA/INB Input Filter
        2. 10.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 10.2.2.3 Gate Driver Output Resistor
        4. 10.2.2.4 Estimate Gate Driver Power Loss
        5. 10.2.2.5 Estimating Junction Temperature
        6. 10.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.6.1 Selecting a VCCI Capacitor
          2. 10.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.6.3 Select a VDDB Capacitor
        7. 10.2.2.7 Dead Time Setting Guidelines
        8. 10.2.2.8 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 認定
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

7.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
CLR External clearance(1) Shortest pin-to-pin distance through air > 8 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surface > 8 mm
DTI Distance through insulation Minimum internal gap (internal clearance) of the double insulation (2 × 10.5 µm) >21 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V
Material group According to IEC 60664-1 I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK
VIOWM Maximum working isolation voltage AC voltage (sine wave); time dependent dielectric breakdown (TDDB), test (See Figure 1) 1500 VRMS
DC voltage 2121 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 sec (qualification)
VTEST = 1.2 × VIOTM, t = 1 s (100% production)		 8000 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)		 8000 VPK
qpd Apparent charge(4) Method a, After Input/Output safety test subgroup 2/3.
Vini = VIOTM, tini = 60s;

Vpd(m) = 1.2 X VIORM = 2545 VPK, tm = 10s

 <5 pC
Method a, After environmental tests subgroup 1.
Vini = VIOTM, tini = 60s;

Vpd(m) = 1.6 X VIORM = 3394 VPK, tm = 10s

 <5

Method b1; At routine test (100% production) and preconditioning (type test)

Vini = 1.2 × VIOTM; tini = 1s;

Vpd(m) = 1.875 * VIORM = 3977 VPK , tm = 1s



 <5
CIO Barrier capacitance, input to output(5) VIO = 0.4 sin (2πft), f =1 MHz 1.2 pF
RIO Isolation resistance, input to output(5) VIO = 500 V at TA = 25°C > 1012 Ω
VIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011
VIO = 500 V at TS =150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 5700 VRMS, t = 60 sec. (qualification),

VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production)

 5700 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.