JAJSE18E March   2017  – May 2021 CC3220MOD , CC3220MODA

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 CC3220MODx and CC3220MODAx Pin Diagram
    2. 7.2 Pin Attributes
      1. 7.2.1 Module Pin Attributes
    3. 7.3 Connections for Unused Pins
    4. 7.4 Pin Attributes and Pin Multiplexing
    5. 7.5 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Chip, but Before Reset Release
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Current Consumption (CC3220MODS and CC3220MODAS)
    5. 8.5  Current Consumption (CC3220MODSF and CC3220MODASF)
    6. 8.6  TX Power and IBAT Versus TX Power Level Settings
    7. 8.7  Brownout and Blackout Conditions
    8. 8.8  Electrical Characteristics
    9. 8.9  CC3220MODAx Antenna Characteristics
    10. 8.10 WLAN Receiver Characteristics
    11. 8.11 WLAN Transmitter Characteristics
    12. 8.12 Reset Requirement
    13. 8.13 Thermal Resistance Characteristics for MOB and MON Packages
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Power-Up Sequencing
      2. 8.14.2 Power-Down Sequencing
      3. 8.14.3 Device Reset
      4. 8.14.4 Wake Up From Hibernate Timing
      5. 8.14.5 Peripherals Timing
        1. 8.14.5.1  SPI
          1. 8.14.5.1.1 SPI Master
          2. 8.14.5.1.2 SPI Slave
        2. 8.14.5.2  I2S
          1. 8.14.5.2.1 I2S Transmit Mode
          2. 8.14.5.2.2 I2S Receive Mode
        3. 8.14.5.3  GPIOs
          1. 8.14.5.3.1 GPIO Input Transition Time Parameters
        4. 8.14.5.4  I2C
        5. 8.14.5.5  IEEE 1149.1 JTAG
        6. 8.14.5.6  ADC
        7. 8.14.5.7  Camera Parallel Port
        8. 8.14.5.8  UART
        9. 8.14.5.9  External Flash Interface
        10. 8.14.5.10 SD Host
        11. 8.14.5.11 Timers
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Arm® Cortex®-M4 プロセッサ・コア・サブシステム
    3. 9.3  Wi-Fi® Network Processor Subsystem
      1. 9.3.1 WLAN
      2. 9.3.2 Network Stack
    4. 9.4  Security
    5. 9.5  Power-Management Subsystem
      1. 9.5.1 VBAT Wide-Voltage Connection
    6. 9.6  Low-Power Operating Mode
    7. 9.7  Memory
      1. 9.7.1 Internal Memory
        1. 9.7.1.1 SRAM
        2. 9.7.1.2 ROM
        3. 9.7.1.3 Flash Memory
        4. 9.7.1.4 Memory Map
    8. 9.8  Restoring Factory Default Configuration
    9. 9.9  Boot Modes
      1. 9.9.1 Boot Mode List
    10. 9.10 Device Certification and Qualification
      1. 9.10.1 FCC Certification and Statement
      2. 9.10.2 Industry Canada (IC) Certification and Statement
      3. 9.10.3 ETSI/CE Certification
      4. 9.10.4 MIC Certification
      5. 9.10.5 SRRC Certification and Statement
    11. 9.11 Module Markings
    12. 9.12 End Product Labeling
    13. 9.13 Manual Information to the End User
  10. 10Applications, Implementation, and Layout
    1. 10.1 Typical Application
    2. 10.2 Device Connection and Layout Fundamentals
      1. 10.2.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.2.2 Reset
      3. 10.2.3 Unused Pins
    3. 10.3 PCB Layout Guidelines
      1. 10.3.1 General Layout Recommendations
      2. 10.3.2 CC3220MODx RF Layout Recommendations
        1. 10.3.2.1 Antenna Placement and Routing
        2. 10.3.2.2 Transmission Line Considerations
      3. 10.3.3 CC3220MODAx RF Layout Recommendations
  11. 11Environmental Requirements and Specifications
    1. 11.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 Baking Conditions
    5. 11.5 Soldering and Reflow Condition
  12. 12Device and Documentation Support
    1. 12.1 Development Tools and Software
    2. 12.2 Firmware Updates
    3. 12.3 Device Nomenclature
    4. 12.4 Documentation Support
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical, Land, and Solder Paste Drawings
    2. 13.2 Package Option Addendum
      1. 13.2.1 Packaging Information
      2. 13.2.2 Tape and Reel Information
        1. 13.2.2.1 CC3220MODx Tape Specifications
        2. 13.2.2.2 CC3220MODAx Tape Specifications

9.7.1.4 Memory Map

Table 9-4 describes the various MCU peripherals and how they are mapped to the processor memory. For more information on peripherals, see the API document.

Table 9-4 Memory Map
START ADDRESS END ADDRESS DESCRIPTION COMMENT
0x0000 0000 0x0007 FFFF On-chip ROM (bootloader + DriverLib)
0x0100 0000 0x010F FFFF On-chip Flash (for user application code) CC3220SF device only
0x2000 0000 0x2003 FFFF Bit-banded on-chip SRAM
0x2200 0000 0x23FF FFFF Bit-band alias of 0x2000 0000 to 0x200F FFFF
0x4000 0000 0x4000 0FFF Watchdog timer A0
0x4000 4000 0x4000 4FFF GPIO port A0
0x4000 5000 0x4000 5FFF GPIO port A1
0x4000 6000 0x4000 6FFF GPIO port A2
0x4000 7000 0x4000 7FFF GPIO port A3
0x4000 C000 0x4000 CFFF UART A0
0x4000 D000 0x4000 DFFF UART A1
0x4002 0000 0x4000 07FF I2C A0 (master)
0x4002 4000 0x4002 4FFF GPIO group 4
0x4002 0800 0x4002 0FFF I2C A0 (slave)
0x4003 0000 0x4003 0FFF General-purpose timer A0
0x4003 1000 0x4003 1FFF General-purpose timer A1
0x4003 2000 0x4003 2FFF General-purpose timer A2
0x4003 3000 0x4003 3FFF General-purpose timer A3
0x400F7000 0x400F 7FFF Configuration registers
0x400F E000 0x400F EFFF System control
0x400F F000 0x400F FFFF µDMA
0x4200 0000 0x43FF FFFF Bit band alias of 0x4000 0000 to 0x400F FFFF
0x4401 0000 0x4401 0FFF SDIO master
0x4401 8000 0x4401 8FFF Camera Interface
0x4401 C000 0x4401 DFFF McASP
0x4402 0000 0x4402 0FFF SSPI Used for external serial Flash
0x4402 1000 0x4402 1FFF GSPI Used by application processor
0x4402 5000 0x4402 5FFF MCU reset clock manager
0x4402 6000 0x4402 6FFF MCU configuration space
0x4402 D000 0x4402 DFFF Global power, reset, and clock manager (GPRCM)
0x4402 E000 0x4402 EFFF MCU shared configuration
0x4402 F000 0x4402 FFFF Hibernate configuration
0x4403 0000 0x4403 FFFF Crypto range (includes apertures for all crypto-related blocks as follows)(1)
0x4403 0000 0x4403 0FFF DTHE registers and TCP checksum(1)
0x4403 5000 0x4403 5FFF MD5/SHA(1)
0x4403 7000 0x4403 7FFF AES(1)
0x4403 9000 0x4403 9FFF DES(1)
0xE000 0000 0xE000 0FFF Instrumentation trace Macrocell™
0xE000 1000 0xE000 1FFF Data watchpoint and trace (DWT)
0xE000 2000 0xE000 2FFF Flash patch and breakpoint (FPB)
0xE000 E000 0xE000 EFFF NVIC
0xE004 0000 0xE004 0FFF Trace port interface unit (TPIU)
0xE004 1000 0xE004 1FFF Reserved for embedded trace macrocell (ETM)
0xE004 2000 0xE00F FFFF Reserved
(1) Additional memory is available in the CC3220SF device (not available in CC3200R device).