JAJSE18 データシート

JAJSE18E March 2017 – May 2021 CC3220MOD , CC3220MODA

PRODUCTION DATA

8.14.5.1.1 SPI Master

The CC3220MODx and CC3220MODAx microcontroller includes one SPI module, which can be configured as a master or slave device. The SPI includes a serial clock with programmable frequency, polarity, and phase; a programmable timing control between chip select and external clock generation; and a programmable delay before the first SPI word is transmitted. Slave mode does not include a dead cycle between two successive words.

Figure 8-8 shows the timing diagram for the SPI master.

Figure 8-8 SPI Master Timing Diagram

Table 8-4 lists the timing parameters for the SPI master.

Table 8-4 SPI Master Timing Parameters

ITEM	NAME	DESCRIPTION	MIN	MAX	UNIT
	F⁽¹⁾	Clock frequency		20	MHz
T2	T_clk⁽¹⁾	Clock period	50		ns
	D⁽¹⁾	Duty cycle	45%	55%
T6	t_IS⁽¹⁾	RX data setup time	1		ns
T7	t_IH⁽¹⁾	RX data hold time	2		ns
T8	t_OD⁽¹⁾	TX data output delay		8.5	ns
T9	t_OH⁽¹⁾	TX data hold time		8	ns

(1) Timing parameter assumes a maximum load of 20 pF.