JAJSE19G October   2017  – November 2022 TUSB564

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-Level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 USB3.1 Modes
      6. 8.4.6 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
      6. 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
      7. 8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
      8. 8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Support for DisplayPort UFP_D Pin Assignment E
      4. 9.2.4 PCB Insertion Loss Curves
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.3.3 4-Level Inputs

The TUSB564 has (I2C_EN, EQ[1:0], DPEQ[1:0], and SSEQ[1:0]) 4-level inputs pins that are used to control the equalization gain and place TUSB564 into different modes of operation. These 4-level inputs utilize a resistor divider to help set the 4 valid levels and provide a wider range of control settings. There is an internal 35 kΩ pull-up and a 95 kΩ pull-down. These resistors, together with the external resistor connection combine to achieve the desired voltage level.

Table 8-1 4-Level Control Pin Settings
LEVELSETTINGS
0Option 1: Tie 1 KΩ 5% to GND.
Option 2: Tie directly to GND.
RTie 20 KΩ 5% to GND.
FFloat (leave pin open)
1Option 1: Tie 1 KΩ 5%to VCC.
Option 2: Tie directly to VCC.
Note:

All four-level inputs are latched on rising edge of internal reset. After tcfg_hd, the internal pull-up and pull-down resistors will be isolated in order to save power.