JAJSE19G October   2017  – November 2022 TUSB564

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-Level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 USB3.1 Modes
      6. 8.4.6 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
      6. 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
      7. 8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
      8. 8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Support for DisplayPort UFP_D Pin Assignment E
      4. 9.2.4 PCB Insertion Loss Curves
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Linear EQ Configuration

Each of the TUSB564 receiver lanes has individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 8-7 details the gain value for each available combination when TUSB564 is in GPIO mode. These same options are also available in I2C mode by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL, EQ2_SEL, and SSEQ_SEL. Each of the 4-bit EQ configuration registers is mapped to the configuration pins as follows: x_SEL = {x1[1:0],x0[1:0]} where xn[1:0] are the EQ configuration pins with pin levels mapped to 2-bit values as: 0 = 00, R = 01, F = 10, 1 = 11.

Table 8-7 TUSB564 Receiver Equalization GPIO Control
Equalization Setting #USB3.1 UPSTREAM FACING PORTSUSB 3.1 DOWNSTREAM FACING PORTALL DISPLAYPORT LANES
EQ1 PIN LEVELEQ0 PIN LEVELEQ GAIN at 2.5 GHz (dB)SSEQ1 PIN LEVELSSEQ0 PIN LEVELEQ GAIN at 2.5 GHz (dB)DPEQ1 PIN LEVELDPEQ0 PIN LEVELEQ GAIN at 4.05 GHz (dB)
000-0.900-2.400-0.3
10R0.20R-1.30R1.6
20F1.20F-0.40F3.0
3012.2010.7014.4
4R03.1R01.5R05.4
5RR4.0RR2.5RR6.5
6RF4.8RF3.2RF7.3
7R15.6R14.0R18.1
8F06.3F04.8F08.9
9FR7.0FR5.5FR9.5
10FF7.5FF6.0FF10.0
11F18.1F16.6F110.6
12108.5107.11011.0
131R9.11R7.61R11.4
141F9.51F8.01F11.8
15119.9118.51112.1