JAJSE19G October   2017  – November 2022 TUSB564

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-Level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 USB3.1 Modes
      6. 8.4.6 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
      6. 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
      7. 8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
      8. 8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Support for DisplayPort UFP_D Pin Assignment E
      4. 9.2.4 PCB Insertion Loss Curves
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Power
PCC-ACTIVE-USBAverage active power in USB-only mode while in U0.CTL1 = L; CTL0 = H; Link in U0 at 5 Gbps;330mW
PCC-ACTIVE-USB-DPAverage active power in USB + 2 lane DP mode.CTL1 = H; CTL0 = H; USB in U0 at 5 Gbps;  DP at 8.1 Gbps;660mW
PCC-ACTIVE-DPAverage active power in 4 lane DP mode.CTL1 = H; CTL0 = L; Four DP lanes at 8.1 Gbps660mW
PCC-NC-USBAverage power in USB mode while in disconnect state.CTL1 = L; CTL0 = H; No USB device detected;2.5mW
PCC-U2U3Average power in USB mode while in U2/U3 stateCTL1 = L; CTL0 = H; Link in U2 or U3;2.5mW
PCC-SHUTDOWNAverage power in Shutdown mode.CTL1 = L; CTL0 = L; I2C_EN = "0";0.7mW
4-State CMOS Inputs(EQ[1:0], SSEQ[1:0], DPEQ[1:0], I2C_EN)
IIHHigh-level input currentVCC = 3.6 V; VIN = 3.6 V2080µA
IILLow-level input currentVCC = 3.6 V; VIN = 0 V-160-40µA
4-Level VTHThreshold 0 / RVCC = 3.3 V0.55V
Threshold R/ FloatVCC = 3.3 V1.65V
Threshold Float / 1VCC = 3.3 V2.7V
RPUInternal pull up resistance45kΩ
RPDInternal pull-down resistance95kΩ
2-State CMOS Input (CTL0, CTL1, FLIP, EN, HPDIN) CTL1, CTL0 and FLIP are Failsafe
VIHHigh-level input voltage23.6V
VILLow-level input voltage00.8V
RPDInternal pull-down resistance for CTL1, CTL0, FLIP, and EN.    500kΩ
IIHHigh-level input currentVIN = 3.6 V-2525µA
IILLow-level input currentVIN = GND, VCC = 3.6 V-2525µA
I2C Control Pins SCL, SDA
VIHHigh-level input voltageI2C_EN ! = 00.7 x VI2C3.6V
VILLow-level input voltageI2C_EN ! = 000.3 × VI2CV
VOLLow-level output voltageI2C_EN ! = 0; IOL = 3 mA00.4V
IOLLow-level output currentI2C_EN ! = 0; VOL = 0.4 V20mA
Ii_I2CInput current on SDA pin0.1 × VI2C < Input voltage < 3.3 V-1010µA
Ci_I2CInput capacitance10pF
USB Differential Receiver (RX1P/N, RX2P/N, SSTXP/N)
VRX-DIFF-PPInput differential peak-peak voltage swing linear dynamic rangeAC-coupled differential peak-to-peak signal measured post CTLE through a reference channel2000mVpp
VRX-DC-CMCommon-mode voltage bias in the receiver (DC)0V
RRX-DIFF-DCDifferential input impedance (DC)Present after a USB3.1 device is detected on TXP/TXN72120Ω
RRX-CM-DCReceiver DC Common Mode impedancePresent after a USB3.1 device is detected on TXP/TXN1830Ω
ZRX-HIGH-IMP-DC-POSCommon-mode input impedance with termination disabled (DC)Present when no USB3.1 device is detected on TXP/TXN. Measured over the range of 0-500 mV with respect to GND.25kΩ
VSIGNAL-DET-DIFF-PPInput Differential peak-to-peak Signal Detect Assert Levelat 5 Gbps, No loss and bit rate PRBS7 pattern70mV
VRX-IDLE-DET-DIFF-PPInput Differential peak-to-peak Signal Detect De-assert Levelat 5 Gbps, No loss and bit rate PRBS7 pattern50mV
VRX-LFPS-DET-DIFF-PPLow-frequency Periodic Signaling (LFPS) Detect ThresholdBelow the minimum is squelched.100300mV
CRXRX input capacitance to GNDAt 2.5 GHz0.51pF
RLRX-DIFFDifferential Return Loss50 MHz – 1.25 GHz at 90 Ω-16dB
2.5 GHz at 90 Ω-17dB
RLRX-CMCommon Mode Return Loss50 MHz – 2.5 GHz at 90 Ω-12dB
EQSSPReceiver equalizationSSEQ[1:0] and EQ[1:0] at 2.5 GHz.12dB
USB Differential Transmitter (TX1P/N, TX2P/N, SSRXP/N)
VTX-DIFF-PPTransmitter dynamic differential voltage swing range.  1300 mVpp
VTX-RCV-DETECTAmount of voltage change allowed during Receiver Detectionat 3.3 V  600mV
VTX-CM-IDLE-DELTATransmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPSmeasured at the connector side of the AC coupling caps with 50 Ω load-600 600mV
VTX-DC-CMCommon-mode voltage bias in the transmitter (DC) 0 2V
VTX-CM-AC-PP-ACTIVETx AC Common-mode voltage activeAt 3.3V; Max mismatch from Txp+Txn for both time and amplitude  100mVpp
VTX-IDLE-DIFF-AC-PPAC Electrical idle differential peak-to-peak output voltageAt package pins0 10mV
VTX-IDLE-DIFF-DCDC Electrical idle differential output voltageAt package pins after low-pass filter to remove AC component0 14mV
VTX-CM-DC-ACTIVE-IDLE-DELTAAbsolute DC common mode voltage between U1 and U0At package pin  200mV
CTXTX input capacitance to GNDAt 2.5 GHz  1.25pF
RTX-DIFFDifferential impedance of the driver 75 120Ω
CAC-COUPLINGAC Coupling capacitor 75 265nF
RTX-CMCommon-mode impedance of the driverMeasured with respect to AC ground over 0-500 mV18 30Ω
ITX-SHORTTX short circuit currentTX± shorted to GND  67mA
RLTX-DIFFDifferential Return Loss50 MHz – 1.25 GHz at 90 Ω -17 dB
RLTX-DIFF-2.5GDifferential Return Loss2.5 GHz at 90 Ω -12 dB
RLTX-CMCommon Mode Return Loss50 MHz – 2.5 GHz at 90 Ω -10 dB
AC Electrical Characteristics for USB and DP
CrosstalkDifferential Cross Talk between TX and RX signal Pairsat 2.5 GHz -27 dB
GLFLow-frequency voltage gain.   at 100 MHz, 600 mVpp VID-2.50.53.5dB
GLF_LFPS_TX1/2Low-frequency voltage gain for SSTX->TX1/TX2 path.    at 10 to 50MHz sine wave; 1.0Vpp VID; EQ = 0; FLIP = 0 and 1;00.81.6dB
CP1 dB-LFLow-frequency 1-dB compression pointat 100 MHz, 200 mVpp < VID < 2000 mVpp1000mVpp
CP1 dB-HFHigh-frequency 1-dB compression pointat 2.5 GHz, 200 mVpp < VID < 2000 mVpp 1000 mVpp
fLFLow-frequency cutoff200 mVpp < VID < 2000 mVpp 2050kHz
DJ_5GTX output deterministic jitter200 mVpp < VID < 2000 mVpp, PRBS7, 5 Gbps 0.04 UIpp
DJ_8.1GTX output deterministic jitter200 mVpp < VID < 2000 mVpp, PRBS7, 8.1 Gbps 0.08 UIpp
TJ_5GTX output total jitter200 mVpp < VID < 2000 mVpp, PRBS7, 5 Gbps 0.07 UIpp
TJ_8.1GTX output total jitter200 mVpp < VID < 2000 mVpp, PRBS7, 8.1 Gbps 0.12 UIpp
DisplayPort Receiver (TX1P/N, TX2P/N, RX1P/N, RX2P/N)
VID_PPPeak-to-peak input differential dynamic voltage range  2000 mV
VICInput Common Mode Voltage 0V
CACAC coupling capacitance 75 265nF
EQDPReceiver EqualizerDPEQ1, DPEQ0 at 4.05 GHz 12 dB
dRData rateHBR3  8.1Gbps
RtiInput Termination resistance 80100120Ω
DisplayPort Transmitter (DP[3:0]P/N)
VTX-DIFFPPVOD dynamic range  1300 mV
ITX-SHORTTX short circuit currentTX± shorted to GND  67mA
AUXP/N and SBU1/2
RONOutput ON resistanceVCC = 3.3 V; VIN = 0 to 0.4 V for AUXP; VIN = 2.7 V to 3.6 V for AUXN 510Ω
RON-MISMATCHΔON resistance mismatch within pairVCC = 3.3 V; VIN = 0 to 0.4 V for AUXP; VIN= 2.7 V to 3.6 V for AUXN  1Ω
RON_FLATON resistance flatness (RONmax–RON min) measured at identical VCC and temperatureVCC = 3.3 V; VIN = 0 to 0.4 V for AUXP; VIN = 2.7 V to 3.6 V for AUXN  2Ω
VAUXP_DC_CMAUX Channel DC common mode voltage for AUXP and SBU2.VCC = 3.3 V0 0.4V
VAUXN_DC_CMAUX Channel DC common mode voltage for AUXN and SBU1VCC = 3.3 V2.7 3.6V
CAUX_ONON-state capacitanceVCC = 3.3 V; CTL1 = 1; VIN = 0 V or 3.3 V 47pF
CAUX_OFFOFF-state capacitanceVCC = 3.3 V; CTL1 = 0; VIN = 0 V or 3.3 V 36pF