JAJSE26 データシート

JAJSE26 October 2017 MSP432E411Y

PRODUCTION DATA.

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾ ⁽²⁾

		MIN	MAX	UNIT
V_DD	V_DD supply voltage	0	4	V
V_DDA	V_DDA supply voltage	0	4	V
V_BAT	V_BAT battery supply voltage	0	4	V
V_BATRMP	V_BAT battery supply voltage ramp time	0	0.7	V/µs
V_{IN_GPIO}	Input voltage ⁽³⁾	–0.3	4	V
I_GPIOMAX	Maximum current per output pin		64	mA
T_S	Unpowered storage temperature range	–65	150	°C
T_JMAX	Maximum junction temperature		125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltages are measured with respect to GND.

(3) Applies to static and dynamic signals including overshoot.

5.2 ESD Ratings

over operating free-air temperature range (unless otherwise noted)

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS‑001 ⁽¹⁾ ⁽³⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22‑C101 ⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

(3) All pins are HBM compliant to ±2000 V for all combinations as per JESD22-A114F, except for the following stress combinations:

The Ethernet EN0RXIN, EN0TXON, EN0RXIP, and EN0TXOP pins to each other.
The GPIO pins PM4, PM5, PM6, and PM7 to other pins.

These exceptions are compliant to 500 V and do not require any special handling beyond typical ESD control procedures during assembly operations per JEDEC publication JEP155. These pins do meet the 500-V CDM specification.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
T_A	Ambient operating temperature range	Extended temperature	–40	105	°C
T_J	Junction operating temperature range	Extended temperature	–40	125	°C

5.4 Recommended DC Operating Conditions

over operating free-air temperature (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_DD	V_DD supply voltage	2.97	3.3	3.63	V
V_DDA	V_DDA supply voltage ⁽¹⁾	2.97	3.3	3.63	V
V_DDC	V_DDC supply voltage, run mode	1.14	1.2	1.32	V
V_DDCDS	V_DDC supply voltage, deep-sleep mode	0.85		0.95	V

(1) To ensure proper operation, power on V_DDA before V_DD if sourced from different supplies, or connect V_DDA to the same supply as V_DD. No restriction exists for powering off.

5.5 Recommended GPIO Operating Characteristics

The following sections describe the recommended GPIO operating characteristics for the device.

Two types of pads are provided on the device:

Fast GPIO pads: These pads provide variable, programmable drive strength and optimized voltage output levels.
Slow GPIO pads: These pads provide 2-mA drive strength and are designed to be sensitive to voltage inputs. The PJ1 GPIOs port pins are slow GPIO pads. All other GPIOs have a fast GPIO pad type.

NOTE

Port pins PL6 and PL7 operate as fast GPIO pads, but have 4-mA drive capability only. GPIO register controls for drive strength, slew rate and open drain have no effect on these pins. The registers which have no effect are as follows: GPIODR2R, GPIODR4R, GPIODR8R, GPIODR12R, GPIOSLR, and GPIOODR.

NOTE

Port pins PM[7:4] operate as fast GPIO pads but support only 2-, 4-, 6-, and 8-mA drive capability. 10- and 12-mA drive are not supported. All standard GPIO register controls, except for the GPIODR12R register, apply to these port pins.

5.6 Recommended Fast GPIO Pad Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_IH	Fast GPIO high-level input voltage		0.65 × V_DD	4	V
I_IH	Fast GPIO high-level input current			300	nA
V_IL	Fast GPIO low-level input voltage		0	0.35 × V_DD	V
I_IL	Fast GPIO low-level input current ⁽²⁾			–200	nA
V_HYS	Fast GPIO input hysteresis		0.49		V
V_OH	Fast GPIO high-level output voltage		2.4		V
V_OL	Fast GPIO low-level output voltage			0.40	V
I_OH	Fast GPIO high-level source current, V_OH = 2.4 V ⁽¹⁾	2-mA drive	2.0		mA
		4-mA drive	4.0
		8-mA drive	8.0
		10-mA drive	10.0
		12-mA drive	12.0
I_OL	Fast GPIO low-level sink current, V_OL = 0.4 V ⁽¹⁾	2-mA drive	2.0		mA
		4-mA drive	4.0
		8-mA drive	8.0
		10-mA drive	10.0
		12-mA drive	12.0
		12-mA drive overdriven to 18 mA	18.0

(1) I_O specifications reflect the maximum current where the corresponding output voltage meets the V_OH or V_OL thresholds. I_O current can exceed these limits (subject to absolute maximum ratings).

(2) Output, pullup, and pulldown are disabled; only input is enabled.

5.7 Recommended Slow GPIO Pad Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IH	Slow GPIO high-level input voltage	0.65 × V_DD	4	V
I_IH	Slow GPIO high-level input current		4.1	nA
V_IL	Slow GPIO low-level input voltage	0	0.35 × V_DD	V
I_IL	Slow GPIO low-level input current ⁽²⁾		–1	nA
V_HYS	Slow GPIO input hysteresis	0.49		V
V_OH	Slow GPIO high-level output voltage	2.4		V
V_OL	Slow GPIO low-level output voltage		0.4	V
I_OH	Slow GPIO high-level source current, V_OH = 2.4 V, 2-mA drive	2.0		mA
I_OL	Slow GPIO low-level sink current, V_OL = 0.4 V ⁽¹⁾, 2-mA drive	2.0		mA

(1) I_O specifications reflect the maximum current where the corresponding output voltage meets the V_OH or V_OL thresholds. I_O current can exceed these limits (subject to absolute maximum ratings).

5.8 GPIO Current Restrictions

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MAX	UNIT
I_MAXL	Cumulative maximum GPIO current per side, left	110	mA
I_MAXB	Cumulative maximum GPIO current per side, bottom ⁽²⁾	116	mA
I_MAXR	Cumulative maximum GPIO current per side, right ⁽²⁾	110	mA
I_MAXT	Cumulative maximum GPIO current per side, top ⁽²⁾	88	mA

(1) Based on design simulations, not tested in production.

(2) Sum of sink and source current for GPIOs as listed in Table 5-1.

Table 5-1 Maximum GPIO Package Side Assignments

SIDE	GPIOs
Left	PB[6-7], PC[4-7], PD[0-3], PE[0-3], PH[0-7], PJ[6-7], PK[0-3], PQ[0-3,7], PR[0-5]
Bottom	PA[0-7], PF[0-7], PG[0-7], PK[4-7], PN[6-7], PR[3,6-7], PQ[5-6], PS[4-7], PT[0-1]
Right	PB[0-3], PJ[2-5], PL[0-5,6-7], PM[0-7], PT[2-3]
Top	PB[4-5], PC[0-3], PD[4-7], PE[4-7], PJ[0-1], PN[0-5], PP[0-7], PQ[4], PS[0-3]

5.9 I/O Reliability

For typical continuous drive applications, I/O pins configured in the range from 2 mA to 12 mA and operating at –40°C to 85°C meet the standard 10-year lifetime reliability. If a continuous current sink of 18 mA is required, then operation is limited to 0 to 75°C to meet the standard 10-year reliability.

At 105°C, I/O pins configured for continuous drive meet the standard 2.5-year lifetime reliability.

In typical switching applications (40% switch rate) operating at –40°C to 85°C, all I/O configurations except 2 mA meet the standard 10-year lifetime reliability with 50-pF loading. By limiting the capacitive loading to 20 pF for an I/O configured to 2 mA, the 10-year lifetime reliability can be met at –40°C to 85°C.

In typical switching applications (40% switch rate) operating at 105°C, all I/O configurations except 2 mA meet the standard 2.5-year lifetime reliability. By reducing the capacitive loading to 20 pF with a typical switching rate at 105°C, a 2-mA I/O configuration meets a 2.5-year lifetime reliability.

5.10 Current Consumption

over operating free-air temperature (unless otherwise noted) ⁽¹⁾

PARAMETER		TEST CONDITIONS	SYSTEM CLOCK		TYP				MAX		UNIT
PARAMETER		TEST CONDITIONS	FREQ	CLOCK SOURCE	–40°C	25°C	85°C	105°C	85°C	105°C ⁽²⁾	UNIT
I_{DD_RUN}	Run mode (flash loop)	V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on including MAC and PHY	120 MHz	MOSC with PLL	96.4	105.3	107.2	108.7	129.9	140.0	mA
			60 MHz	MOSC with PLL	67.4	76.6	78.6	79.9	100.3	112.5
			16 MHz	PIOSC	11.9	24.4	25.5	26.7	45.0	56.4
			1 MHz	PIOSC	5.75	10.9	12.1	13.3	31.3	42.6
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on including MAC but not PHY	120 MHz	MOSC with PLL	69.9	77.8	79.6	80.8	98.8	108.4
			60 MHz	MOSC with PLL	40.9	49.2	50.9	52.1	69.2	80.8
			16 MHz	PIOSC	11.3	23.6	25.0	26.2	43.1	54.3
			1 MHz	PIOSC	5.10	10.1	11.5	12.7	29.3	40.5
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on except MAC and PHY	120 MHz	MOSC with PLL	68.1	76.0	77.6	78.6	96.6	106.0
			60 MHz	MOSC with PLL	40.0	48.2	49.8	50.8	67.9	79.2
			16 MHz	PIOSC	11.1	23.3	24.6	25.6	42.5	53.3
			1 MHz	PIOSC	5.07	10.1	11.3	12.3	29.0	39.8
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All off	120 MHz	MOSC with PLL	35.2	39.1	40.4	41.5	55.8	65.3
			60 MHz	MOSC with PLL	23.2	29.4	30.7	31.7	45.8	55.5
			16 MHz	PIOSC	7.38	17.9	19.0	20.0	34.5	44.1
			1 MHz	PIOSC	4.12	9.13	10.3	11.4	25.7	35.5
	Run mode (SRAM loop)	V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on including MAC and PHY	120 MHz	MOSC with PLL	93.8	103.6	111.6	113.2	133.4	144.6
			60 MHz	MOSC with PLL	66.9	76.7	78.7	80.0	100.0	111.9
			16 MHz	PIOSC	12.6	19.0	20.1	21.3	39.1	50.3
			1 MHz	PIOSC	5.73	10.6	11.7	12.8	30.9	42.2
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on including MAC but not PHY	120 MHz	MOSC with PLL	67.2	76.1	84.0	85.4	102.3	113.0
			60 MHz	MOSC with PLL	40.3	49.2	50.9	52.2	68.9	80.2
			16 MHz	PIOSC	11.9	18.2	19.6	20.8	37.2	48.2
			1 MHz	PIOSC	5.08	9.79	11.2	12.3	28.9	40.1
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals =All on except MAC and PHY	120 MHz	MOSC with PLL	65.4	74.3	82.0	83.2	100.1	110.6
			60 MHz	MOSC with PLL	39.4	48.2	49.8	50.9	67.6	78.6
			16 MHz	PIOSC	11.7	17.9	19.2	20.2	36.6	47.2
			1 MHz	PIOSC	5.05	9.75	11.0	11.9	28.6	39.4
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All off	120 MHz	MOSC with PLL	35.4	43.3	44.7	45.8	59.8	69.0
			60 MHz	MOSC with PLL	23.4	29.4	30.7	31.7	45.5	54.9
			16 MHz	PIOSC	7.08	12.4	13.6	14.6	28.7	38.0
			1 MHz	PIOSC	4.60	8.78	10.0	11.0	25.3	34.9
I_{DD_SLEEP}	Sleep mode (FLASHPM = 0x0)	V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on including MAC and PHY, LDO = 1.2 V	120 MHz	MOSC with PLL	82.8	94.8	96.8	98.1	117.9	129.1	mA
			60 MHz	MOSC with PLL	60.8	69.2	71.2	72.3	91.8	102.9
			16 MHz	PIOSC	11.2	16.8	18.1	19.1	35.4	45.9
			1 MHz	PIOSC ⁽³⁾	5.10	10.3	11.5	12.6	28.9	39.6
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on including MAC but not PHY, LDO = 1.2 V	120 MHz	MOSC with PLL	56.2	67.4	69.1	70.3	87.1	97.8
			60 MHz	MOSC with PLL	34.4	41.9	43.4	44.5	60.7	71.6
			16 MHz	PIOSC ⁽³⁾	10.6	16.2	17.5	18.5	34.5	45.1
			1 MHz	PIOSC ⁽³⁾	4.47	9.60	10.9	12.0	28.0	38.7
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on except MAC and PHY, LDO = 1.2 V	120 MHz	MOSC with PLL	54.4	65.6	67.1	68.1	84.9	95.4
			60 MHz	MOSC with PLL	33.5	40.9	42.3	43.2	59.4	70.0
			16 MHz	PIOSC ⁽³⁾	10.4	15.9	17.1	17.9	33.9	44.1
			1 MHz	PIOSC ⁽³⁾	4.44	9.56	10.7	11.6	27.7	38.0
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All off, LDO = 1.2 V	120 MHz	MOSC with PLL	22.0	28.6	29.8	30.7	44.1	53.1
			60 MHz	MOSC with PLL	16.3	22.0	23.2	24.1	37.5	46.6
			16 MHz	PIOSC ⁽³⁾	5.37	10.4	11.5	12.4	26.1	35.1
			1 MHz	PIOSC ⁽³⁾	4.37	8.60	9.71	10.6	24.6	33.9
	Sleep mode (FLASHPM = 0x2)	V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on including MAC and PHY, LDO = 1.2 V	120 MHz	MOSC with PLL	86.5	89.0	91.2	92.5	112.1	123.5
			60 MHz	MOSC with PLL	61.6	63.4	65.6	66.7	86.0	97.2
			16 MHz	PIOSC ⁽³⁾	10.4	11.1	12.4	13.5	29.8	40.4
			1 MHz	PIOSC ⁽³⁾	4.45	4.49	5.83	6.98	23.4	34.2
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on including MAC but not PHY, LDO = 1.2 V	120 MHz	MOSC with PLL	59.9	61.7	63.4	64.7	81.3	92.1
			60 MHz	MOSC with PLL	35.1	36.1	37.8	38.9	54.9	66.0
			16 MHz	PIOSC ⁽³⁾	9.75	10.4	11.8	12.9	28.9	39.6
			1 MHz	PIOSC ⁽³⁾	3.82	3.82	5.25	6.38	22.5	33.4
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on except MAC and PHY, LDO = 1.2 V	120 MHz	MOSC with PLL	58.1	59.9	61.4	62.5	79.1	89.7
			60 MHz	MOSC with PLL	34.2	35.1	36.7	37.6	53.6	64.4
			16 MHz	PIOSC ⁽³⁾	9.50	10.1	11.4	12.3	28.3	38.6
			1 MHz	PIOSC ⁽³⁾	3.79	3.78	5.06	5.96	22.2	32.7
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All off, LDO = 1.2 V	120 MHz	MOSC with PLL	22.0	22.8	24.1	25.1	38.2	47.4
			60 MHz	MOSC with PLL	15.7	16.2	17.5	18.5	31.7	40.9
			16 MHz	PIOSC ⁽³⁾	4.50	4.60	5.80	6.80	20.5	29.8
			1 MHz	PIOSC ⁽³⁾	3.00	2.80	4.10	5.20	19.1	28.7
I_{DD_DEEPSLEEP}	Deep-sleep mode (FLASHPM = 0x2)	V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on, LDO = 1.2 V	16 MHz	PIOSC	9.74	9.78	10.8	11.6	24.1	32.1	mA
			30 kHz	LFIOSC	2.60	2.83	3.83	4.60	17.1	25.3
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All off, LDO = 1.2 V	16 MHz	PIOSC	4.53	4.05	4.88	5.53	15.9	22.7
			30 kHz	LFIOSC	0.614	0.762	1.69	2.46	13.3	20.7
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on, LDO = 0.9 V	16 MHz	PIOSC	5.21	7.33	7.97	8.48	15.3	20.1
			30 kHz	LFIOSC	2.02	2.16	2.79	3.29	10.0	14.9
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All off, LDO = 0.9 V ⁽⁴⁾	16 MHz	PIOSC	1.08	3.10	3.61	4.01	9.50	13.4
			30 kHz	LFIOSC	0.367	0.454	0.954	1.36	6.86	10.8
I_{DDA_RUN}, I_{DDA_SLEEP}	All run modes	V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on	120 MHz	MOSC with PLL	2.61	2.66	2.68	2.66	3.03	3.35	mA
			60 MHz	MOSC with PLL	2.61	2.66	2.68	2.66	3.04	3.10
			16 MHz	PIOSC	2.45	2.49	2.50	2.48	2.85	2.95
			1 MHz	PIOSC	2.45	2.48	2.50	2.48	2.84	2.90
	All sleep modes	V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All off	120 MHz	MOSC with PLL	0.227	0.229	0.270	0.250	0.559	0.650
			60 MHz	MOSC with PLL	0.229	0.232	0.267	0.250	0.579	0.600
			16 MHz	PIOSC	0.228	0.229	0.265	0.251	0.545	0.575
			1 MHz	PIOSC	0.227	0.227	0.267	0.247	0.549	0.555
I_{DDA_DEEPSLEEP}	Deep-sleep mode (FLASHPM = 0x2)	V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on, LDO = 1.2 V	16 MHz	PIOSC	2.45	2.48	2.50	2.48	2.84	2.90	mA
			30 kHz	LFIOSC	2.45	2.48	2.50	2.48	2.85	2.90
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All off, LDO = 1.2 V	16 MHz	PIOSC	0.226	0.227	0.265	0.249	0.558	0.635
			30 kHz	LFIOSC	0.228	0.227	0.272	0.247	0.558	0.600
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All on, LDO = 0.9 V ⁽⁴⁾	16 MHz	PIOSC	2.14	2.42	2.44	2.42	2.78	2.88
			30 kHz	LFIOSC	2.44	2.42	2.44	2.42	2.86	2.88
		V_DD = 3.3 V, V_DDA = 3.3 V, Peripherals = All off, LDO = 0.9 V ⁽⁴⁾	16 MHz	PIOSC	0.216	0.166	0.209	0.193	0.563	0.580
			30 kHz	LFIOSC	0.223	0.167	0.209	0.189	0.508	0.580
I_{HIB_NORTC}	Hibernate mode (external wake, RTC disabled)	V_BAT = 3.0 V V_DD = 0 V, V_DDA = 0 V, System clock = OFF, Hibernate module = 32.768 kHz			1.04	1.20	1.44	1.69	1.62	2.14	µA
I_{HIB_RTC}	Hibernate mode (RTC enabled)	V_BAT = 3.0 V, V_DD = 0 V, V_DDA = 0 V, System clock = OFF, Hibernate module = 32.768 kHz			1.12	1.29	1.54	1.82	1.75	2.33	µA
I_{HIB_VDD3ON}	Hibernate mode (VDD3ON mode, tamper enabled)	V_BAT = 3.0 V, V_DD = 3.3 V, V_DDA = 3.3 V, System clock = OFF, Hibernate module = 32.768 kHz			6.78	7.99	17.0	22.1	31.0	46.2	µA
I_{HIB_VDD3ON}	Hibernate mode (VDD3ON mode, tamper disabled)	V_BAT = 3.0 V, V_DD = 3.3 V, V_DDA = 3.3 V, System clock = OFF, Hibernate module = 32.768 kHz			5.42	6.39	15.4	17.8	28.9	32.0	µA

(1) Section 5.11 lists the current consumption that specific peripherals contribute to the run mode current consumption in Section 5.10. If these peripherals are not powered, then the peripheral current consumption can be subtracted from the run mode consumption in Section 5.10.

(2) Applicable to extended temperature devices only.

(3) If the MOSC is the source of the run-mode system clock and is powered down in sleep mode, wake time is increased by t_{MOSC_SETTLE}.

(4) See the System Control chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual for information on lowering the LDO voltage to 0.9 V.

5.11 Peripheral Current Consumption

over operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	SYSTEM CLOCK	TYP	UNIT
I_DDUSB	USB (including USB PHY) run mode current	V_DD = 3.3 V, V_DDA = 3.3 V	120 MHz (MOSC with PLL)	4.0	mA
I_DDEMAC	Ethernet MAC run mode current	V_DD = 3.3 V, V_DDA = 3.3 V	120 MHz (MOSC with PLL)	1.9	mA
I_DDEMACPHY	Ethernet MAC and PHY run mode current	V_DD = 3.3 V, V_DDA = 3.3 V	120 MHz (MOSC with PLL)	30	mA

5.12 LDO Regulator Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER		MIN	TYP	MAX	UNIT
C_LDO	External filter capacitor size for internal power supply⁽¹⁾	2.5		4.0	µF
ESR	Filter capacitor equivalent series resistance	0		100	mΩ
ESL	Filter capacitor equivalent series inductance			0.5	nH
V_LDO	LDO output voltage, run mode	1.13	1.2	1.27	V
I_INRUSH	Inrush current	50		250	mA

(1) Connect the capacitor as close as possible to pin E10.

5.13 Power Dissipation

over operating free-air temperature (unless otherwise noted) ⁽¹⁾ ⁽²⁾

PARAMETER		T_A	T_J	MIN	MAX	UNIT
P_DE	Extended temperature device power dissipation	105°C (extended temperature part)	125°C (extended temperature part)		509	mW

(1) If the device exceeds the power dissipation value shown, then modifications such as heat sinks or fans must be used to conform to the limits shown.

(2) A larger power dissipation allowance can be achieved by lowering T_A as long as T_JMAX shown in Section 5.1 is not exceeded.

5.14 Thermal Resistance Characteristics, 212-Pin ZAD (NFBGA) Package

over operating free-air temperature range (unless otherwise noted)

THERMAL METRIC		VALUE	UNIT
θ_JA	Thermal resistance (junction to ambient) ⁽¹⁾	39.3	°C/W
θ_JB	Thermal resistance (junction to board) ⁽¹⁾	18.6	°C/W
θ_JC	Thermal resistance (junction to case) ⁽¹⁾	12.9	°C/W
Ψ_JT	Thermal metric (junction to top of package)	0.2	°C/W
Ψ_JB	Thermal metric (junction to board)	18.4	°C/W
T_J	Junction temperature formula	T_C + (P × Ψ_JT) ⁽²⁾ T_PCB + (P × Ψ_JB) ⁽³⁾ T_A + (P × θ_JA) ⁽⁴⁾ T_B + (P × θ_JB) ⁽⁵⁾ ⁽⁶⁾	°C

(1) Junction to ambient thermal resistance (θ_JA), junction to board thermal resistance (θ_JB), and junction to case thermal resistance (θ_JC) numbers are determined by a package simulator.

(2) T_C is the case temperature and P is the device power consumption.

(3) T_PCB is the temperature of the board acquired by following the steps listed in the EAI/JESD 51-8 standard summarized in Semiconductor and IC Package Thermal Metrics. P is the device power consumption.

(4) Because θ_JA is highly variable and based on factors such as board design, chip size, pad size, altitude, and external ambient temperature, TI recommends using the equations that contain Ψ_JT and Ψ_JB for best results.

(5) T_B is temperature of the board.

(6) θ_JB is not a pure reflection of the internal resistance of the package because it includes the resistance of the testing board and environment. TI recommends using equations that contain Ψ_JT and Ψ_JB for best results.

5.15 Timing and Switching Characteristics

5.15.1 Load Conditions

Table 5-2 shows the load conditions used for timing measurements, and Table 5-2 lists the load values for the specified signals.

Figure 5-1 Load Conditions

Table 5-2 Load Conditions

SIGNALS	LOAD VALUE (C_L)
LCDDATA[23:0]	25 pF
EPI0S[35:0] SDRAM interface	30 pF
EPI0S[35:0] general-purpose interface
EPI0S[35:0] host-bus interface
EPI0S[35:0] PSRAM interface	40 pF
All other digital I/O signals	50 pF

5.15.2 Power Supply Sequencing

To ensure proper operation, power on V_DDA before V_DD if sourced from different supplies, or connect V_DDA to the same supply as V_DD. No restriction exists for powering off.

5.15.2.1 Power and Brownout

Table 5-3 Power and Brownout Levels

over operating free-air temperature (unless otherwise noted)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
P1	t_{VDDA_RISE}	Analog supply voltage (V_DDA) rise time			∞	µs
P2	t_{VDD_RISE}	I/O supply voltage (V_DD) rise time			∞	µs
P3	t_{VDDC_RISE}	Core supply voltage (V_DDC) rise time	10		150	µs
P4	V_POR	Power-on reset threshold (rising edge)	1.98	2.35	2.72	V
		Power-on reset threshold (falling edge)	1.84	2.20	2.56
		Power-on reset hysteresis	0.06	0.15	0.24
P5	V_{DDA_POK}	V_DDA power-OK threshold (rising edge)	2.67	2.82	2.97	V
P6	V_{DDA_BOR0}	V_DDA brownout reset threshold	2.71	2.80	2.89	V
P7	V_{DD_POK}	V_DD power-OK threshold (rising edge)	2.65	2.80	2.90	V
P7	V_{DD_POK}	V_DD power-OK threshold (falling edge)	2.67	2.76	2.85	V
P8	V_{DD_BOR0}	V_DD brownout reset threshold	2.77	2.86	2.95	V
P9	V_{DDC_POK}	V_DDC power-OK threshold (rising edge)	0.85	0.95	1.10	V
P9	V_{DDC_POK}	V_DDC power-OK threshold (falling edge)	0.71	0.80	0.85	V

5.15.2.1.1 V_DDA Levels

The V_DDA supply has three monitors:

Power-on reset (POR)
Power-OK (POK)
Brownout reset (BOR)

The POR monitor is used to keep the analog circuitry in reset until the V_DDA supply reaches the correct range for the analog circuitry to begin operating. The POK monitor is used to keep the digital circuitry in reset until the V_DDA power supply is at an acceptable operational level. The digital reset is only released when the Power-On Reset has deasserted and the Power-OK monitor for each supply indicates that power levels are in operational ranges. The BOR monitor is used to generate a reset to the device or assert an interrupt if the V_DDA supply drops below its operational range.

NOTE

V_DDA BOR and V_DD BOR events are a combined BOR to the system logic, such that if either BOR event occurs, the following bits are affected:

The BORRIS bit in the Raw Interrupt Status (RIS) register, System Control offset 0x050
The BORMIS bit in the Masked Interrupt Status and Clear (MISC) register, System Control offset 0x058. This bit is set only if the BORIM bit in the Interrupt Mask Control (IMC) register has been set.
The BOR bit in the Reset Cause (RESC) register, System Control offset 0x05C. This bit is set only if either of the BOR events have been configured to initiate a reset.

In addition, the following bits control both BOR events:

The BORIM bit in the Interrupt Mask Control (IMC) register, System Control offset 0x054
The VDDA_UBOR0 and VDD_UBOR0 bits in the Power-Temperature Cause (PWRTC) register

See the System Control chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual for more information on how to configure these registers.

Figure 5-2 shows the relationship between V_DDA, POK, POR, and a BOR event.

Figure 5-2 Power and Brownout Assertions vs V_DDA Levels

5.15.2.1.2 V_DD Levels

The V_DD supply has two monitors:

Power-OK (POK)
Brownout reset (BOR)

The POK monitor is used to keep the digital circuitry in reset until the V_DD power supply reaches an acceptable operational level. The digital reset is only released when the POR has deasserted and the POK monitor for each supply indicates that power levels are in operational ranges. The BOR monitor is used to generate a reset to the device or assert an interrupt if the V_DD supply drops below its operational range.

NOTE

V_DDA BOR and V_DD BOR events are a combined BOR to the system logic, such that if either BOR event occurs, the following bits are affected:

The BORRIS bit in the Raw Interrupt Status (RIS) register, System Control offset 0x050
The BORMIS bit in the Masked Interrupt Status and Clear (MISC) register, System Control offset 0x058. This bit is set only if the BORIM bit in the Interrupt Mask Control (IMC) register has been set.
The BOR bit in the Reset Cause (RESC) register, System Control offset 0x05C. This bit is set only if either of the BOR events have been configured to initiate a reset.

In addition, the following bits control both BOR events:

The BORIM bit in the Interrupt Mask Control (IMC) register, System Control offset 0x054
The VDDA_UBOR0 and VDD_UBOR0 bits in the Power-Temperature Cause (PWRTC) register

See the System Control chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual for more information on how to configure these registers.

Figure 5-3 shows the relationship between V_DD, POK, POR, and a BOR event.

Figure 5-3 Power and Brownout Assertions vs V_DD Levels

5.15.2.1.3 V_DDC Levels

The V_DDC supply has one monitor, the Power-OK (POK). The POK monitor is used to keep the digital circuitry in reset until the V_DDC power supply reaches an acceptable operational level. The digital reset is only released when the power-on reset has deasserted and the POK monitor for each supply indicates that power levels are in operational ranges. Figure 5-4 shows the relationship between POK and V_DDC.

Figure 5-4 POK Assertion vs V_DDC

5.15.2.1.4 V_DD Glitch Response

Figure 5-5 shows the response of the BOR and the POR circuit to glitches on the VDD supply.

MSP432E411Y Snowflake_A0_Glitch_Response.png

Figure 5-5 POR-BOR V_DD Glitch Response

5.15.2.1.5 V_DD Droop Response

Figure 5-6 shows the response of the BOR and the POR monitors to a drop on the VDD supply.

MSP432E411Y Snowflake_A0_Droop_Response.png

Figure 5-6 POR-BOR V_DD Droop Response

5.15.3 Reset Timing

Table 5-4 lists the reset characteristics.

Table 5-4 Reset Characteristics

over operating free-air temperature (unless otherwise noted)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
R1	t_DPORDLY	Digital POR to internal reset assertion delay (see Figure 5-7)	0.44		126	µs
R2	t_IRTOUT ⁽¹⁾ ⁽²⁾	Standard internal reset time		14	16	ms
R2	t_IRTOUT ⁽¹⁾ ⁽²⁾	Internal reset time with recovery code repair (program or erase)⁽³⁾	24.4		6400⁽⁷⁾	ms
R3	t_BOR0DLY ⁽¹⁾	BOR0 to internal reset assertion delay ⁽⁶⁾ (see Figure 5-8)	0.44		125	µs
R4	t_RSTMIN	Minimum RST pulse duration		0.25⁽⁴⁾ or 100⁽⁵⁾		µs
R5	t_IRHWDLY	RST to internal reset assertion delay (see Figure 5-9)		0.85		µs
R6	t_IRSWR ⁽¹⁾	Internal reset time-out after software-initiated system reset (see Figure 5-10)		2.44		µs
R7	t_IRWDR ⁽¹⁾	Internal reset time-out after watchdog reset (see Figure 5-11)		2.44		µs
R8	t_IRMFR ⁽¹⁾	Internal reset time-out after MOSC failure reset (see Figure 5-12)		2.44		µs

(1) These values are based on simulation.

(2) This is the delay from the time POR is released until the reset vector is fetched.

(3) This parameter applies only in situations where a power-loss or brownout event occurs during an EEPROM program or erase operation, and EEPROM must be repaired (which is a rare case). For all other sequences, there is no change to normal POR timing. This delay is in addition to other POR delays.

(4) Standard operation

(5) Deep-sleep operation with PIOSC powered down

(6) Timing values depend on the V_DD power-down ramp rate.

(7) This value represents the maximum internal reset time when the EEPROM reaches its endurance limit.

Figure 5-7 Digital Power-On Reset Timing

The digital power-on reset is released only when the analog power-on reset has deasserted and the Power-OK monitor for each supply indicates that power levels are in operational ranges.

Figure 5-8 Brownout Reset Timing

Figure 5-9 External Reset Timing (RST)

Figure 5-10 Software Reset Timing

Figure 5-11 Watchdog Reset Timing

Figure 5-12 MOSC Failure Reset Timing

5.15.4 Clock Specifications

The following sections provide specifications on the various clock sources and mode.

5.15.4.1 PLL Specifications

Table 5-5 lists the PLL characteristics.

NOTE

If the integrated Ethernet PHY is used, f_{REF_XTAL} and f_{REF_EXT} must be 25 MHz.

Table 5-5 Phase Locked Loop (PLL) Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER			MIN	MAX	UNIT
f_{REF_XTAL}	Crystal reference		5	25	MHz
f_{REF_EXT}	External clock reference		5	25	MHz
f_PLLR	PLL VCO frequency at 1.2 V⁽²⁾		100	480	MHz
f_PLLS	PLL VCO frequency at 0.9 V⁽¹⁾		100	480	MHz
t_READY	PLL lock time	Enabling the PLL, when PLL is transitioning from power down to power up		512 × (reference clock period)	µs
		When the PLL VCO frequency is changed (PLL is already enabled)		128 × (reference clock period)
		Changing the OSCSRC between MOSC and PIOSC		128 × (reference clock period)

(1) If the LDO is dropped to 0.9 V, the system must be run 1/4 of the maximum frequency at most. The Q value in the PLLFREQ1 register must be set to 0x3 rather than using the PSYSDIV field in the RSCLKCFG register for the divisor.

(2) PLL frequency is manually calculated using the values in the PLLFREQ0 and PLLFREQ1 registers.

5.15.4.1.1 PLL Configuration

The PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency and enables the PLL to drive the output. The PLL is controlled using the PLLFREQ0, PLLFREQ1, and PLLSTAT registers. Changes made to these registers do not become active until after the NEWFREQ bit in the RSCLKCFG register is enabled. The clock source for the main PLL is selected by configuring the PLLSRC field in the Run and Sleep Clock Configuration (RSCLKCFG) register. The PLL allows for the generation of system clock frequencies in excess of the reference clock provided. The reference clocks for the PLL are the PIOSC and the MOSC.

The PLL is controlled by two registers, PLLFREQ0 and PLLFREQ1. The PLL VCO frequency (f_VCO) is determined through Equation 1.

Equation 1. f_VCO = f_IN × MDIV

where

f_IN = f_XTAL / (Q+1)(N+1) or f_PIOSC / (Q+1)(N+1)
MDIV = MINT + (MFRAC / 1024)

The Q and N values are programmed in the PLLFREQ1 register. To reduce jitter, program MFRAC to 0x0.

When the PLL is active, the system clock frequency (SysClk) is calculated using Equation 2.

Equation 2. SysClk = f_VCO / (1 + 1)

The PLL system divisor factor (PSYSDIV) must be set as 1. Table 5-6 lists examples of the system clock frequency.

Table 5-6 Examples of System Clock Frequencies

f_VCO (MHz)	Q	PSYSDIV + 1	System Clock (SYSCLK) Frequency (MHz)
480	2	2	120
480	3	2	80
480	4	2	60
480	5	2	48
320	2	2	80
320	3	2	53
320	4	2	40

If the main oscillator provides the clock reference to the PLL, the translation provided by hardware and used to program the PLL is available for software in the PLL Frequency n (PLLFREQn) registers. The internal translation provides a translation within ±1% of the targeted PLL VCO frequency. Table 5-7 shows the actual PLL frequency and error for a given crystal choice.

Table 5-7 provides examples of the programming expected for the PLLFREQ0 and PLLFREQ1 registers. The CRYSTAL FREQUENCY column specifies the input crystal frequency and the PLL FREQUENCY column displays the PLL frequency given the values of MINT and N, when Q = 0.

Table 5-7 Actual PLL Frequency⁽¹⁾

CRYSTAL FREQUENCY (MHz)	MINT		N	REFERENCE FREQUENCY (MHz)⁽²⁾	PLL FREQUENCY (MHz)
CRYSTAL FREQUENCY (MHz)	DECIMAL VALUE	HEXADECIMAL VALUE	N	REFERENCE FREQUENCY (MHz)⁽²⁾	PLL FREQUENCY (MHz)
5	64	0x40	0x0	5	320
6	160	0x35	0x2	2	320
8	40	0x28	0x0	8	320
10	32	0x20	0x0	10	320
12	80	0x50	0x2	4	320
16	20	0x14	0x0	16	320
18	160	0xA0	0x8	2	320
20	16	0x10	0x0	20	320
24	40	0x28	0x2	8	320
25	64	0x40	0x4	5	320
5	96	0x60	0x0	5	480
6	80	0x50	0x0	6	480
8	60	0x3C	0x0	8	480
10	48	0x30	0x0	10	480
12	40	0x28	0x0	12	480
16	30	0x1E	0x0	16	480
18	80	0x50	0x2	6	480
20	24	0x18	0x0	20	480
24	20	0x14	0x0	24	480
25	96	0x60	0x4	5	480

(1) For all examples listed, Q = 0.

(2) For a given crystal frequency, N should be chosen such that the reference frequency is 4 to 30 MHz.

5.15.4.2 PIOSC Specifications

Table 5-8 lists the PIOSC characteristics.

Table 5-8 PIOSC Clock Characteristics

PARAMETER		MAX	UNIT
f_PIOSC	Factory calibration, 0°C to 105°C: Internal 16-MHz precision oscillator frequency variance across voltage and temperature range when factory calibration is used	±6%
	Factory calibration, –40°C to <0°C	±10%
	Recalibration: Internal 16-MHz precision oscillator frequency variance when recalibration is used at a specific temperature	±1%
t_START	PIOSC start-up time⁽¹⁾	1	µs

(1) PIOSC start-up time is part of reset and is included in the internal reset time-out value (T_IRTOUT) in Table 5-4. The T_START value is based on simulation.

5.15.4.3 Low-Frequency Oscillator Specifications

Table 5-9 lists the characteristics of the low-frequency oscillator.

Table 5-9 Low-Frequency Oscillator Characteristics

PARAMETER		MIN	NOM	MAX	UNIT
f_LFIOSC	Internal low-frequency oscillator frequency	10	33	75	kHz

5.15.4.4 Hibernation Low-Frequency Oscillator Specifications

Table 5-10 Hibernation External Oscillator (XOSC) Input Characteristics

PARAMETER		MIN	NOM	MAX	UNIT
f_HIBXOSC ⁽¹⁾	Parallel resonance frequency		32.768		kHz
C₁, C₂	External load capacitance on XOSC0, XOSC1 pins ⁽²⁾	12		24	pF
C_PKG	Device package stray shunt capacitance ⁽²⁾		0.5		pF
C_PCB	PCB stray shunt capacitance ⁽²⁾		0.5		pF
C_SHUNT	Total shunt capacitance ⁽²⁾			4	pF
ESR	Crystal effective series resistance, OSCDRV = 0 ⁽³⁾			50	kΩ
ESR	Crystal effective series resistance, OSCDRV = 1 ⁽³⁾			75	kΩ
DL	Oscillator output drive level			0.25	µW
t_START	Oscillator start-up time, when using a crystal ⁽⁵⁾		600	1500 ⁽⁴⁾	ms
V_IH	CMOS input high level, when using an external oscillator with V_Supply > 3.3 V	2.64			V
V_IH	CMOS input high level, when using an external oscillator with 1.8 V ≤ V_Supply ≤ 3.3 V	0.8 × V_Supply			V
V_IL ⁽⁶⁾	CMOS input low level, when using an external oscillator with 1.8 V ≤ V_Supply ≤ 3.63 V			0.2 × V_Supply	V
V_HYS ⁽⁶⁾	CMOS input buffer hysteresis, when using an external oscillator with 1.8 V ≤ V_Supply ≤ 3.63 V	360	960	1390	mV
DC_{HIBOSC_EXT}	External single-ended (bypass) reference duty cycle	30%		70%

(1) The Hibernation XOSC pins are not fail-safe and must follow the limits in Section 5.15.9.1.2.

(2) See the additional information about the load capacitors following this table.

(3) Crystal ESR specified by crystal manufacturer.

(4) Only valid for recommended supply conditions. Measured with OSCDRV bit set (high drive strength enabled, 24 pF).

(5) Oscillator start-up time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation such that the internal clock is valid.

(6) Specification is relative to the larger of V_DD or V_BAT.

Choose the load capacitors added on the board, C₁ and C₂, such that Equation 3 is satisfied (see Table 5-10 for typical values).

Equation 3. C_L = (C₁ × C₂) / (C₁ + C₂) + C_SHUNT

where

C_L = load capacitance specified by crystal manufacturer
C_SHUNT = C_PKG + C_PCB + C₀ (total shunt capacitance seen across XOSC0 and XOSC1)
C_PKG, C_PCB as measured across the XOSC0 and XOSC1 pins excluding the crystal
Clear the OSCDRV bit in the Hibernation Control (HIBCTL) register for C_1,2 ≤ 18 pF
Set the OSCDRV bit for C_1,2 > 18 pF
C₀ = Shunt capacitance of crystal specified by the crystal manufacturer

Table 5-11 lists the characteristics of the Hibernation module low-frequency oscillator.

Table 5-11 Hibernation Internal Low-Frequency Oscillator Clock Characteristics

PARAMETER		MIN	NOM	MAX	UNIT
f_HIBLFIOSC	Internal low-frequency hibernation oscillator frequency	10	33	90	kHz

5.15.4.5 Main Oscillator Specifications

Table 5-12 lists the required characteristics of the main oscillator input.

Table 5-12 Main Oscillator Input Characteristics

over operating free-air temperature (unless otherwise noted)⁽²⁾

PARAMETER			MIN	NOM	MAX	UNIT
f_MOSC	Parallel resonance frequency		4 ⁽¹⁾		25	MHz
f_{REF_XTAL_BYPASS}	External clock reference (PLL in BYPASS mode)		0		120	MHz
C₁, C₂	External load capacitance on OSC0, OSC1 pins ⁽³⁾		12		24	pF
C_PKG	Device package stray shunt capacitance ⁽³⁾			0.5		pF
C_PCB	PCB stray shunt capacitance ⁽³⁾			0.5		pF
C_SHUNT	Total shunt capacitance ⁽³⁾				4	pF
ESR	Crystal effective series resistance	4 MHz ⁽⁴⁾ ⁽⁵⁾			300	Ω
		6 MHz ⁽⁴⁾ ⁽⁵⁾			200
		8 MHz ⁽⁴⁾ ⁽⁵⁾			130
		12 MHz ⁽⁴⁾ ⁽⁵⁾			120
		16 MHz ⁽⁴⁾ ⁽⁵⁾			100
		25 MHz ⁽⁴⁾ ⁽⁵⁾			50
DL	Oscillator output drive level⁽⁷⁾			OSC_PWR		mW
T_START	Oscillator start-up time, when using a crystal ⁽⁶⁾				18	ms
V_IH	CMOS input high level, when using an external oscillator		0.65 × V_DD		V_DD	V
V_IL	CMOS input low level, when using an external oscillator		GND		0.35 × V_DD	V
V_HYS	CMOS input buffer hysteresis, when using an external oscillator		150			mV
DC_{OSC_EXT}	External clock reference duty cycle		45%		55%

(1) 5 MHz is the minimum when using the PLL.

(2) See Table 5-39 and Table 5-40 for additional Ethernet crystal requirements.

(3) See the additional information about the load capacitors following this table.

(4) Crystal ESR specified by crystal manufacturer.

(5) Crystal vendors can be contacted to confirm these specifications are met for a specific crystal part number if the vendors generic crystal datasheet show limits outside of these specifications.

(6) Oscillator start-up time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation such that the internal clock is valid.

(7) OSC_PWR = (2 × π × F_P × C_L × 2.5)² × ESR / 2. An estimation of the typical power delivered to the crystal is based on the C_L, F_P and ESR parameters of the crystal in the circuit as calculated by the OSC_PWR equation. Ensure that the value calculated for OSC_PWR does not exceed the crystal's drive-level maximum.

The load capacitors added on the board, C₁ and C₂, should be chosen such that Equation 4 is satisfied (see Table 5-12 for typical values and Table 5-13 for detailed crystal parameter information).

Equation 4. C_L = (C₁ × C₂) / (C₁ + C₂) + C_SHUNT

where

C_L = load capacitance specified by crystal manufacturer
C_SHUNT = C₀ + C_PKG + C_PCB (total shunt capacitance seen across OSC0 and OSC1 crystal inputs)
C_PKG, C_PCB = Mutual capacitance as measured across the OSC0 and OSC1 pins excluding the crystal
C₀ = Shunt capacitance of crystal specified by the crystal manufacturer

Table 5-13 lists part numbers of crystals that have been simulated and confirmed to operate within the specifications in Table 5-12. Other crystals that have nearly identical crystal parameters can be expected to work as well.

In Table 5-13, the crystal parameters labeled C0, C1, and L1 are values that are obtained from the crystal manufacturer. These numbers are usually a result of testing a relevant batch of crystals on a network analyzer. The parameters labeled ESR, DL, and C_L are maximum numbers usually available in the data sheet for a crystal.

Table 5-13 also includes three columns of Recommended Component Values. These values apply to system board components. C₁ and C₂ are the values in picofarads of the load capacitors that should be put on each leg of the crystal pins to ensure oscillation at the correct frequency. R_s is the value in kΩ of a resistor that is placed in series with the crystal between the OSC1 pin and the crystal pin. R_s dissipates some of the power so the Max Dl crystal parameter is not exceeded. Only use the recommended C₁, C₂, and R_s values with the associated crystal part. The values in the table were used in the simulation to ensure crystal start-up and to determine the worst-case drive level (WC DL). The value in the WC DL column should not be greater than the Max DL crystal parameter. The WC DL value can be used to determine if a crystal with similar parameter values but a lower Max DL value is acceptable.

Table 5-13 Crystal Parameters

Manufacturer	Manufacturer Part Number	Holder	Package Size (mm × mm)	Frequency (MHz)	Crystal Specification (Tolerance / Stability)	Crystal Parameters						Recommended Component Values			WC DL (µW)
						Typical Values			Max Values			Recommended Component Values
						C0 (pF)	C1 (fF)	L1 (mH)	ESR (Ω)	Max DL (µW)	C_L (pf)	C₁ (pF)	C₂ (pF)	R_s (kΩ)
NDK	NX8045GB-4.000M-STD-CJL-5	NX8045GB	8 × 4.5	4	30 / 50 ppm	1.00	2.70	598.10	300	500	8	12	12	0	132
FOX	FQ1045A-4	2-SMD	10 × 4.5	4	30 / 30 ppm	1.18	4.05	396.00	150	500	10	14	14	0	103
NDK	NX8045GB-5.000M-STD-CSF-4	NX8045GB	8 × 4.5	5	30 / 50 ppm	1.00	2.80	356.50	250	500	8	12	12	0	164
NDK	NX8045GB-6.000M-STD-CSF-4	NX8045GB	8 × 4.5	6	30 / 50 ppm	1.30	4.10	173.20	250	500	8	12	12	0	214
FOX	FQ1045A-6	2-SMD	10 × 4.5	6	30 / 30 ppm	1.37	6.26	112.30	150	500	10	14	14	0	209
NDK	NX8045GB-8.000M-STD-CSF-6	NX8045GB	8 × 4.5	8	30 / 50 ppm	1.00	2.80	139.30	200	500	8	12	12	0	277
FOX	FQ7050B-8	4-SMD	7 × 5	8	30 / 30 ppm	1.95	6.69	59.10	80	500	10	14	14	0	217
ECS	ECS-80-16-28A-TR	HC49/US	12.5 × 4.85	8	50 / 30 ppm	1.82	4.90	85.70	80	500	16	24	24	0	298
Abracon	AABMM-12.0000MHz-10-D-1-X-T	ABMM	7.2 × 5.2	12	10 / 20 ppm	2.37	8.85	20.5	50	500	10	12	12	2.0 ⁽¹⁾	124
NDK	NX3225GA-12.000MHZ-STD-CRG-2	NX3225GA	3.2 × 2.5	12	20 / 30 ppm	0.70	2.20	81.00	100	200	8	12	12	2.5	147
NDK	NX5032GA-12.000MHZ-LN-CD-1	NX5032GA	5 × 3.2	12	30 / 50 ppm	0.93	3.12	56.40	120	500	8	12	12	0	362
FOX	FQ5032B-12	4-SMD	5 × 3.2	12	30 / 30 ppm	1.16	4.16	42.30	80	500	10	14	14	0	370
Abracon	AABMM-16.0000MHz-10-D-1-X-T	ABMM	7.2 × 5.2	16	10 / 20 ppm	3.00	11.00	9.30	50	500	10	12	12	2.0 ⁽¹⁾	143
Ecliptek	ECX-6595-16.000M	HC-49/UP	13.3 × 4.85	16	15 / 30 ppm	3.00	12.7	8.1	50	1000	10	12	12	2.0 ⁽¹⁾	139
NDK	NX3225GA-16.000MHZ-STD-CRG-2	NX3225GA	3.2 × 2.5	16	20 / 30 ppm	1.00	2.90	33.90	80	200	8	12	12	2	188
NDK	NX5032GA-16.000MHZ-LN-CD-1	NX5032GA	5 × 3.2	16	30 / 50 ppm	1.02	3.82	25.90	120 ⁽²⁾	500	8	10	10	0	437
ECS	ECS-160-9-42-CKM-TR	ECX-42	4 × 2.5	16	10 / 10 ppm	1.47	3.90	25.84	60	300	9	12	12	0.5	289
Abracon	AABMM-25.0000MHz-10-D-1-X-T	ABMM	7.2 × 5.2	25	10 / 20 ppm	3.00	11.00	3.70	50	500	10	12	12	2.0 ⁽¹⁾	158
Ecliptek	ECX-6593-25.000M	HC-49/UP	13.3 × 4.85	25	15 / 30 ppm	3.00	12.8	3.2	40	1000	10	12	12	1.5 ⁽¹⁾	159
NDK	NX3225GA-25.000MHZ-STD-CRG-2	NX3225GA	3.2 × 2.5	25	20 / 30 ppm	1.10	4.70	8.70	50	200	8	12	12	2	181
NDK	NX5032GA-25.000MHZ-LD-CD-1	NX5032GA	5 × 3.2	25	30 / 50 ppm	1.3	5.1	7.1	70	500	8	10	10	1.0 ⁽¹⁾	216
NDK	NX5032GA-25.000MHZ-LD-CD-1	NX5032GA	5 × 3.2	25	30 / 50 ppm	1.3	5.1	7.1	70	500	8	12	12	0.75 ⁽³⁾	269
AURIS	Q-25.000M-HC3225/4-F-30-30-E-12-TR	HC3225/4	3.2 × 2.5	25	30 / 30 ppm	1.58	5.01	8.34	50	500	12	16	16	1	331
FOX	FQ5032B-25	4-SMD	5 × 3.2	25	30 / 30 ppm	1.69	7.92	5.13	50	500	10	14	14	0.5	433
TXC	7A2570018	NX5032GA	5 × 3.2	25	20 / 25 ppm	2.0	6.7	6.1	30	350	10	12	12	2.0 ⁽³⁾	124

(1) R_S values as low as 0 Ω can be used. Using a lower R_S value causes the WC DL to increase toward the maximum DL of the crystal.

(2) Although this ESR value is outside of the recommended crystal ESR maximum for this frequency, this crystal has been simulated to confirm proper operation and is valid for use with this device.

(3) R_S values as low as 500 Ω can be used. Using a lower R_S value causes the WC DL to increase toward the maximum DL of the crystal.

5.15.4.6 Main Oscillator Specification WIth ADC

Table 5-14 lists the system clock characteristics with ADC operation.

Table 5-14 System Clock Characteristics With ADC Operation

PARAMETER		MIN	NOM	MAX	UNIT
f_sysadc	System clock frequency when the ADC module is operating (when PLL is bypassed)		16		MHz

5.15.4.7 System Clock Characteristics With USB Operation

Table 5-15 lists the system clock characteristics with USB operation.

Table 5-15 System Clock Characteristics With USB Operation

PARAMETER		MIN	NOM	MAX	UNIT
f_sysusb	System clock frequency when the USB module is operating (MOSC must be the clock source, either with or without using the PLL)	30			MHz

5.15.5 Sleep Modes

The following tables can be used to calculate the maximum wake time from sleep or deep sleep mode, depending on the specific application. Depending on the application configuration, each parameter, except for t_FLASH, adds sequential latency to the wake time. Flash restoration happens in parallel to the other wake processes, and its wake time is normally absorbed by the other latencies. As an example, the wake time for a device in deep sleep mode with the PIOSC and PLL turned off and the flash and SRAM in low-power mode is calculated by Equation 5.

Equation 5. Wake Time = t_PIOSCDS + t_PLLDS + t_SRAMLPDS

t_FLASH does not contribute to this equation because the values of the other parameters are greater.

In sleep mode, the wake time due to a clock source is zero because the device uses the same clock configuration in run mode; thus, there is no latency involved with respect to the clocks.

Table 5-16 lists the wake-up times from sleep mode.

Table 5-16 Wake From Sleep Characteristics

over operating free-air temperature (unless otherwise noted)

NO.	PARAMETER		MAX	UNIT
D1	t_PIOSC	Time to restore PIOSC as system clock in sleep mode	N/A	µs
D2	t_MOSC	Time to restore MOSC as system clock in sleep mode	N/A	µs
D3	t_PLL	Time to restore PLL as system clock in sleep mode	N/A	µs
D4	t_LDO	Time to restore LDO to 1.2 V in sleep mode	39	µs
D5	t_FLASH	Time to restore flash to active state from low-power state in sleep mode	96	µs
D6	t_SRAMLP	Time to restore SRAM to active state from low-power state in sleep mode	15	µs
D7	t_SRAMSTBY	Time to restore SRAM to active state from standby state in sleep mode	15	µs

Table 5-16 lists the wake-up times from deep sleep mode.

Table 5-17 Wake From Deep Sleep Characteristics

over operating free-air temperature (unless otherwise noted)

NO.	PARAMETER		MAX	UNIT
D8	t_PIOSCDS	Time to restore PIOSC as system clock in deep sleep mode	14	deep-sleep clock cycles
D9	t_MOSCDS	Time to restore MOSC as system clock in deep sleep mode	18	ms
D10	t_PLLDS	Time to restore PLL as system clock in deep sleep mode	1 cycle of deep sleep clock + 512 cycles of PLL reference clock ⁽¹⁾	clock cycles
D11	t_LDODS	Time to restore LDO to 1.2 V in deep sleep mode	39	µs
D12	t_FLASHLPDS	Time to restore flash to active state from low-power state	96	µs
D13	t_SRAMLPDS	Time to restore SRAM to active state from low-power state	15	µs
D14	t_SRAMSTBYDS	Time to restore SRAM to active state from standby state	15	µs

(1) Deep sleep clock can vary. See the System Control chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual for the deep sleep clock options.

5.15.6 Hibernation Module

The Hibernation module requires special system implementation considerations because it is intended to power down all other sections of its host device. See the Hibernation Module chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual.

Table 5-18 lists the required characteristics of the Hibernation module battery.

Table 5-18 Hibernation Module Battery Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER			MIN	NOM	MAX	UNIT
V_BAT	Battery supply voltage		1.8	3.0	3.6	V
V_BATRMP	V_BAT battery supply voltage ramp time		0		0.7	V/µs
V_LOWBAT	Low-battery detect voltage	VBATSEL = 0x0	1.8	1.9	2.0	V
		VBATSEL = 0x1	2.0	2.1	2.2
		VBATSEL = 0x2	2.2	2.3	2.4
		VBATSEL = 0x3	2.4	2.5	2.6

Table 5-19 lists the timing characteristics of the HIB module.

Table 5-19 Hibernation Module Characteristics

over operating free-air temperature (unless otherwise noted) (see Figure 5-13)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
H1	t_WAKE	WAKE assertion time	100			ns
H2	t_{WAKE_TO_HIB}	WAKE assert to HIB desassert (wake-up time)			1	HIB module clock period
H3	t_{VDD_RAMP}	V_DD ramp to 3.0 V		See ⁽¹⁾		µs
H4	t_{VDD_CODE}	V_DD at 3 V to internal POR deassert; first instruction executes			500	µs
H5	DC_RTCCLK	Duty cycle for RTCCLK output signal, when using a 32.768‑kHz crystal	40%		60%
H5	DC_RTCCLK	Duty cycle for RTCCLK output signal, when using a 32.768‑kHz external single-ended (bypass) clock source	30%		70%

(1) Depends on characteristics of power supply.

Figure 5-13 Hibernation Module Timing

Table 5-20 lists the characteristics of the HIB module tamper detection.

Table 5-20 Hibernation Module Tamper I/O Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER		MIN	TYP	MAX	UNIT
R_TPU	TMPRn pullup resistor	3.5	4.4	5.2	MΩ
t_SP	TMPRn pulse duration with short glitch filter	62			µs
t_LP	TMPRn pulse duration with long glitch filter	94			ms
t_NMIS	TMPRn assertion to NMI (short glitch filter)			95	µs
t_NMIL	TMPRn assertion to NMI (long glitch filter)			94	ms
V_IH	TMPRn high-level input voltage when operating from V_BAT	V_BAT × 0.8			V

5.15.7 Flash Memory

Table 5-21 lists the characteristics of the flash memory.

Table 5-21 Flash Memory Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER			MIN	TYP	MAX	UNIT
PE_CYC	Number of program and erase cycles		100000			cycles
t_RET	Data retention with 100% power-on hours at T_J = 85°C		20			years
t_{RET_EXTEMP}	Data retention with 10% power-on hours at T_J = 125°C and 90% power-on hours at T_J = 100°C		11			years
t_PROG64	Program time for double-word-aligned (64 bits) data		30	100	300	µs
t_ERASE	Page erase time	<1k cycles		8	15	ms
		10k cycles		15	40
		100k cycles		75	500
t_ME	Mass erase time	<1k cycles		10	25	ms
		10k cycles		20	70
		100k cycles		300	2500

5.15.8 EEPROM

Table 5-22 lists the characteristics of the EEPROM.

Table 5-22 EEPROM Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER			MIN	TYP	MAX	UNIT
EPE_CYC	Number of mass program and erase cycles of a single word		500000			cycles
ET_RET	Data retention with 100% power-on hours at T_J = 85°C		20			years
ET_{RET_EXTEMP}	Data retention with 10% power-on hours at T_J = 125°C and 90% power-on hours at T_J = 100°C		11			years
ET_PROG	Program time for 32 bits of data with memory space available			110	600	µs
	Program time for 32 bits of data in which a copy to the copy buffer is required, the copy buffer has space, and less than 10% of EEPROM endurance used			30		ms
	Program time for 32 bits of data in which a copy to the copy buffer is required, the copy buffer has space, and more than 90% of EEPROM endurance used				900
	Program time for 32 bits of data in which a copy of the copy buffer is required, the copy buffer requires an erase, and less than 10% of EEPROM endurance used			60
	Program time for 32 bits of data a copy to the copy buffer is required, the copy buffer requires an erase, and more than 90% of EEPROM endurance used				1800
ET_READ	Read access time			7 + 2EWS	9 + 4EWS	system clock cycles
ET_ME	Mass erase time	<1k cycles		8	15	ms
		10k cycles		15	40
		100k cycles		75	500

5.15.9 Input/Output Pin Characteristics

NOTE

All GPIO signals are 3.3-V tolerant, except for PB1 (USB0VBUS) which is 5-V tolerant. See the General-Purpose Input/Outputs (GPIOs) chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual for more information on GPIO configuration.

Two types of pads are provided on the device:

Fast GPIO pads: These pads provide variable, programmable drive strength and optimized voltage output levels.
Slow GPIO pads: These pads provide 2-mA drive strength and are designed to be sensitive to voltage inputs. The following GPIOs port pins are designed with slow GPIO pads:
- PJ1

NOTE

Port pins PL6 and PL7 operate as fast GPIO pads, but have 4-mA drive capability only. GPIO register controls for drive strength, slew rate, and open drain have no effect on these pins. The following registers have no effect: GPIODR2R, GPIODR4R, GPIODR8R, GPIODR12R, GPIOSLR, and GPIOODR.

NOTE

Port pins PM[7:4] operate as fast GPIO pads but support only 2-, 4-, 6-, and 8-mA drive capability. All standard GPIO register controls, except for the GPIODR12R register, apply to these port pins.

Table 5-23 lists the characteristics of the fast GPIOs.

Table 5-23 Fast GPIO Module Characteristics

over operating free-air temperature (unless otherwise noted) ⁽¹⁾ ⁽²⁾ ⁽³⁾ ⁽⁴⁾

PARAMETER			MIN	TYP	MAX	UNIT
C_LGPIO	Capacitive loading for measurements given in this table ⁽⁵⁾				50	pF
R_GPIOPU	Fast GPIO internal pullup resistor ⁽⁶⁾		12.1	16.0	20.2	kΩ
R_GPIOPU4MA	Fast GPIO PL6 and PL7 (4 mA only) pullup resistor		25		40	kΩ
R_GPIOPD	Fast GPIO internal pulldown resistor ⁽⁶⁾		13.0	20.5	35.5	kΩ
R_GPIOPD4MA	Fast GPIO PL6 and PL7 (4 mA only) pulldown resistor		10	14.3	17	kΩ
I_LKG+	Fast GPIO input leakage current, 0 V ≤ V_IN ≤ V_DD GPIO pins⁽⁷⁾				400	nA
I_LKG+	Fast GPIO input leakage current, 0 V < V_IN ≤ V_DD, fast GPIO pins configured as ADC or analog comparator inputs				400	nA
I_INJ-	DC injection current, V_IN ≤ 0 V				60	µA
I_MAXINJ-	Maximum negative injection if not voltage protected ⁽⁴⁾				–0.5	mA
t_GPIOR	Fast GPIO rise time⁽⁸⁾	2-mA drive		7.85	11.73	ns
		4-mA drive		4.15	6.35
		8-mA drive		2.33	3.73
		8-mA drive with slew rate control		3.77	5.76
		10-mA drive		1.98	3.22
		12-mA drive		1.75	2.9
t_GPIOF	Fast GPIO fall time ⁽⁹⁾	2-mA drive		10.3	16.5	ns
		4-mA drive		5.15	8.29
		8-mA drive		2.58	4.16
		8-mA drive with slew rate control		3.54	5.55
		10-mA drive		2.07	3.34
		12-mA drive		1.73	2.78

(1) V_DD must be within the range specified in Section 5.4.

(2) Leakage and Injection current characteristics specified in this table also apply to XOSC0 and XOSC1 inputs.

(3) For the external reference inputs of the ADC, avoid a current-limiting resistor (see the I_VREF specification in Table 5-33).

(4) I/O pads should be protected if the I/O voltage may go outside the limits shown in the table. If the part is unpowered, the I/O pad voltage or current must be limited (as shown in this table) to avoid powering the part through the I/O pad, which can potentially cause irreversible damage.

(5) See the individual peripheral sections for specific loading information.

(6) This value includes all GPIO except for port pins PL6 and PL7.

(7) The leakage current is measured with V_IN applied to the corresponding pins. The leakage of digital port pins is measured individually. The port pin is configured as an input and the pullup/pulldown resistor is disabled.

(8) Time measured from 20% to 80% of V_DD.

(9) Time measured from 80% to 20% of V_DD.

Table 5-24 lists the characteristics of the slow GPIOs.

Table 5-24 Slow GPIO Module Characteristics

over operating free-air temperature (unless otherwise noted)⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		MIN	TYP	MAX	UNIT
C_LGPIO	Capacitive loading for measurements given in this table⁽⁴⁾			50	pF
R_GPIOPU	Slow GPIO internal pullup resistor	13.8	20.0	31.4	kΩ
R_GPIOPD	Slow GPIO internal pulldown resistor	13.0	20.5	35.5	kΩ
I_LKG+	Slow GPIO input leakage current, 0 V ≤ V_IN ≤ V_DD, GPIO pins⁽⁵⁾			3.25	nA
I_LKG+	Slow GPIO input leakage current, 0 V < V_IN ≤ V_DD, GPIO pins configured as ADC or analog comparator inputs			3.25	nA
I_INJ-	DC injection current, V_IN ≤ 0 V			3.42	µA
t_GPIOR	Slow GPIO rise time, 2-mA drive⁽⁶⁾		19.3	29.8	ns
t_GPIOF	Slow GPIO fall time, 2-mA drive⁽⁷⁾		12.8	21.1	ns

(1) V_DD must be within the range specified in Section 5.4.

(2) V_IN must be within the range specified in Section 5.1. Leakage current outside of this maximum voltage is not ensured and can result in permanent damage of the device.

(3) To avoid potential damage to the part, externally limit either the voltage or current on the I/Os other than power and WAKE as listed in this table.

(4) See the individual peripheral sections for specific loading information.

(5) The leakage current is measured with V_IN applied to the corresponding pins. The leakage of digital port pins is measured individually. The port pin is configured as an input and the pullup/pulldown resistor is disabled.

(6) Time measured from 20% to 80% of V_DD.

(7) Time measured from 80% to 20% of V_DD.

5.15.9.1 Types of I/O Pins and ESD Protection

CAUTION

All device I/Os pins, except for PB1, are NOT 5-V tolerant; voltages in excess of the limits in Section 5.4 can permanently damage the device. PB1 is used for the USB0VBUS signal, which requires a 5-V input.

5.15.9.1.1 Hibernate WAKE pin

The Hibernate WAKE pin uses ESD protection, similar to the one shown in Figure 5-14. This ESD protection prevents a direct path between this pad and any power supply rails in the device. The WAKE pad input voltage should be kept inside the maximum ratings specified in Section 5.1 to ensure current leakage and current injections are within acceptable range. Table 5-25 lists current leakages and current injection for these pins.

Figure 5-14 ESD Protection

Table 5-25 Pad Voltage and Current Characteristics for Hibernate WAKE Pin

over operating free-air temperature (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER		MAX	UNIT
I_LKG+	Positive I/O leakage for V_DD ≤ V_IN ≤ V_BAT + 0.3 V	300	nA
I_LKG-	Negative I/O leakage for –0.3 V ≤ V_IN ≤ 0 V⁽³⁾	43.3	µA
I_INJ+	Maximum positive injection if not voltage protected	2	mA
I_INJ-	Maximum negative injection if not voltage protected ⁽⁴⁾	–0.5	mA

(1) V_IN must be within the range specified in Section 5.1. Leakage current outside of this maximum voltage is not ensured and can result in permanent damage of the device.

(2) VDD must be within the range specified in Section 5.4.

(3) Leakage outside the minimum range (–0.3 V) is unbounded and must be limited to I_INJ- using an external resistor.

(4) If the I/O pad is not voltage limited, it should be current limited (to I_INJ + and I_INJ-) if there is any possibility of the pad voltage exceeding the V_IO limits (including transient behavior during supply ramp up, or at any time when the part is unpowered).

5.15.9.1.2 Nonpower I/O Pins

Most nonpower I/Os (with the exception of the I/O pad for Hibernate WAKE input) have ESD protection as shown in Figure 5-15.

These I/Os have an ESD clamp to ground and a diode connection to the corresponding power supply rail. To prevent potential damage to the device, follow the specifications in Table 5-26 for the voltage and current of these I/Os. In addition, comply with that the ADC external reference specifications in Table 5-33 to prevent gain error.

Figure 5-15 ESD Protection for Nonpower Pins (Except WAKE Signal)

Table 5-26 Nonpower I/O Pad Voltage and Current Characteristics

over operating free-air temperature (unless otherwise noted) ⁽¹⁾ ⁽²⁾ ⁽³⁾

PARAMETER		MIN	TYP	MAX	UNIT
V_IO	I/O pad voltage limits if voltage protected	–0.3	V_DD	V_DD + 0.3	V
I_LKG+	Positive I/O leakage for V_DD ≤ V_IN ≤V_IO ⁽⁴⁾			400	nA
I_LKG-	Negative I/O leakage for V_IO MIN ≤ V_IN ≤ 0V ⁽⁴⁾			60	µA
I_INJ+	Maximum positive injection if not voltage protected⁽⁵⁾			2	mA
I_INJ-	Maximum negative injection if not voltage protected⁽⁵⁾			–0.5	mA

(1) To avoid potential damage to the part, externally limit either the voltage or current on I/Os other than power and WAKE as listed in this table.

(2) For the external reference inputs of the ADC, avoid a current-limiting resistor (see the I_VREF specification in Table 5-33).

(3) I/O pads should be protected if at any point the I/O voltage has a possibility of going outside the limits shown in the table. If the part is unpowered, the I/O pad voltage and current must be limited (as shown in this table) to avoid powering the part through the I/O pad, which can potentially cause irreversible damage.

(4) MIN and MAX leakage current for the case when the I/O is voltage protected to V_IO MIN or V_IO MAX.

(5) If the I/O pad is not voltage limited, it should be current limited (to I_INJ+ and I_INJ-) if there is any possibility of the pad voltage exceeding the V_IO limits (including transient behavior during supply ramp up, or at any time when the part is unpowered).

5.15.10 External Peripheral Interface (EPI)

Table 5-27 lists the load conditions used to characterize the EPI interface.

Table 5-27 EPI Interface Load Conditions

SIGNALS	LOAD VALUE (C_L)
EPI0S[35:0] SDRAM interface	30 pF
EPI0S[35:0] General-Purpose interface
EPI0S[35:0] Host-Bus interface
EPI0S[35:0] PSRAM interface	40 pF

When the EPI module is in SDRAM mode, EPI CLK (EPI0S31) must be configured to 12 mA. The EPI data bus can be configured to 8 mA. Table 5-28 lists the rise and fall times in SDRAM mode.

Table 5-28 EPI SDRAM Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_SDRAMR	EPI rise time (from 20% to 80% of V_DD)	12-mA drive, C_L = 30 pF		2	3	ns
t_SDRAMF	EPI fall time (from 80% to 20% of V_DD)	12-mA drive, C_L = 30 pF		2	3	ns

Table 5-29 lists the switching characteristics of the SDRAM interface.

Table 5-29 EPI SDRAM Interface Characteristics

over operating free-air temperature (unless otherwise noted) ⁽¹⁾ (see Figure 5-16, Figure 5-17, and Figure 5-18)

NO.	PARAMETER		MIN	MAX	UNIT
E1	t_CK	SDRAM clock period	16.67		ns
E2	t_CH	SDRAM clock high time	8.33		ns
E3	t_CL	SDRAM clock low time	8.33		ns
E4	t_COV	CLK to output valid		4	ns
E5	t_COI	CLK to output invalid		4	ns
E6	t_COT	CLK to output tristate		4	ns
E7	t_S	Input set up to CLK	8.5		ns
E8	t_H	CLK to input hold	0		ns
E9	t_PU	Power-up time	100		µs
E10	t_RP	Precharge all banks	20		ns
E11	t_RFC	Auto refresh	66		ns
E12	t_MRD	Program mode register	2		EPI CLK

(1) The EPI SDRAM interface must use 12-mA drive.

MSP432E411Y epi_sdram_init_lode_mode_reg.gif

1. If CS is high at clock high time, all applied commands are NOP.

2. The Mode register can be loaded before the autorefresh cycles.

3. JEDEC and PC100 specify 3 clock cycles.

4. Outputs are Hi-Z after the command is issued.

Figure 5-16 SDRAM Initialization and Load Mode Register Timing

Figure 5-17 SDRAM Read Timing

Figure 5-18 SDRAM Write Timing

Table 5-30 lists the characteristics of the Host-Bus 8 and Host-Bus 16 interface.

Table 5-30 EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics

over operating free-air temperature (unless otherwise noted) (see Figure 5-19, Figure 5-20, Figure 5-21, and Figure 5-22)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
E14	t_ISU	Read data set up time	10			ns
E15	t_IH	Read data hold time	0			ns
E16	t_DV	WRn to write data valid			3.6	ns
E17	t_DI	Data hold from WRn invalid	1			EPI clock cycles
E18	t_OV	ALE/CSn to output valid			4	ns
E19	t_OINV	CSn to output invalid			4	ns
E20	t_STLOW	WRn / RDn strobe duration low	1			EPI clock cycles
E21	t_ALEHIGH	ALE duration high		1		EPI clock cycles
E22	t_CSLOW	CSn duration low	2			EPI clock cycles
E23	t_ALEST	ALE rising to WRn / RDn strobe falling	2			EPI clock cycles
E24	t_ALEADD	ALE falling to Address high impedance	1			EPI clock cycles

Figure 5-19 Host-Bus 8/16 Asynchronous Mode Read Timing

Figure 5-20 Host-Bus 8/16 Asynchronous Mode Write Timing

Figure 5-21 Host-Bus 8/16 Mode Asynchronous Muxed Read Timing

Figure 5-22 Host-Bus 8/16 Mode Asynchronous Muxed Write Timing

Table 5-31 lists the switching characteristics of the general-purpose interface.

Table 5-31 EPI General-Purpose Interface Characteristics

over operating free-air temperature (unless otherwise noted) (see Figure 5-23)

NO.	PARAMETER		MIN	MAX	UNIT
E25	t_CK	General-purpose clock period	16.67		ns
E26	t_CH	General-purpose clock high time	8.33		ns
E27	t_CL	General-purpose clock low time	8.33		ns
E28	t_ISU	Input signal set up time to rising clock edge	8.50		ns
E29	t_IH	Input signal hold time from rising clock edge	0		ns
E30	t_DV	Falling clock edge to output valid		4	ns
E31	t_DI	Falling clock edge to output invalid		4	ns

NOTE:

This figure shows accesses when the FRM50 bit is clear, the FRMCNT field is 0x0, and the WR2CYC bit is clear.

Figure 5-23 General-Purpose Mode Read and Write Timing

Table 5-32 lists the switching characteristics of the PSRAM interface.

Table 5-32 EPI PSRAM Interface Characteristics

over operating free-air temperature (unless otherwise noted) (see Figure 5-24 and Figure 5-25)

NO.	PARAMETER		MIN	MAX	UNIT
E33	t_EPICLK	EPI_CLK period	20		ns
E34	t_RTFT	EPI_CLK rise or fall time		1.8	ns
E35	t_OV	Falling EPI_CLK to address/write data or control output valid ⁽¹⁾	4.5	20	ns
E36	t_HT	Falling EPI_CLK to address/write data or control hold time ⁽¹⁾	2		ns
E37	t_SUP	Read data setup time from EPI_CLK rising		9	ns
E38	t_DH	Read data output hold from EPI_CLK rising	0		ns
E39	t_IRV	iRDY setup time		9	ns
E40	t_IRH	iRDY hold time		9	ns

(1) Control output includes WRn, RDn, OEn, BSELn, ALE, and CSn.

Figure 5-24 PSRAM Single Burst Read

Figure 5-25 PSRAM Single Burst Write

5.15.11 Analog-to-Digital Converter (ADC)

Table 5-33 lists the electrical characteristics for the ADC at 1 Msps.

Table 5-33 Electrical Characteristics for ADC at 1 Msps

V_REF+ = 3.3 V, f_ADC = 16 MHz (unless otherwise noted)⁽¹⁾

PARAMETER		MIN	TYP	MAX	UNIT
Power supply requirements
V_DDA	ADC supply voltage	2.97	3.3	3.63	V
GNDA	ADC ground voltage		0		V
VDDA and GNDA voltage reference
C_REF	Voltage reference decoupling capacitance		1.0 // 0.01 ⁽²⁾		µF
External voltage reference input
V_REFA+	Positive external voltage reference for ADC, when VREF field in the ADCCTL register is 0x1⁽³⁾	2.4	V_DDA	V_DDA	V
V_REFA-	Negative external voltage reference for ADC, when VREF field in the ADCCTL register is 0x1⁽³⁾	GNDA	GNDA	0.3	V
I_VREF	Current on VREF+ input, using external V_REF+ = 3.3 V		330.5	440	µA
I_LVREF	DC leakage current on VREF+ input when external VREF disabled			2.0	µA
C_REF	External reference decoupling capacitance ⁽³⁾		1.0 // 0.01 ⁽²⁾		µF
Analog input
V_ADCIN	Single-ended, full-scale analog input voltage, internal reference ⁽⁴⁾ ⁽⁵⁾	0		V_DDA	V
	Differential, full-scale analog input voltage, internal reference ⁽⁴⁾⁽⁶⁾	–V_DDA		V_VDDA
	Single-ended, full-scale analog input voltage, external reference ⁽³⁾ ⁽⁵⁾	V_REFA-		V_REFA+
	Differential, full-scale analog input voltage, external reference⁽³⁾⁽⁷⁾	–(V_REFA+ – V_REFA-)		V_REFA+ – V_REFA-
VIN_CM	Input common-mode voltage, differential mode⁽⁸⁾			[(V_REFA+ + V_REFA-) / 2] ±0.025	V
I_L	ADC input leakage current⁽⁹⁾			2.0	µA
R_ADC	ADC equivalent input resistance ⁽⁹⁾			2.5	kΩ
C_ADC	ADC equivalent input capacitance ⁽⁹⁾			10	pF
R_S	Analog source resistance ⁽⁹⁾			500	Ω
Sampling dynamics
f_ADC	ADC conversion clock frequency⁽¹⁰⁾		16		MHz
f_CONV	ADC conversion rate		1		Msps
t_S	ADC sample time		250		ns
t_C	ADC conversion time ⁽¹¹⁾		1		µs
t_LT	Latency from trigger to start of conversion		2		ADC clock cycles
System performance when using external reference ⁽¹²⁾ ⁽¹³⁾
N	Resolution		12		bits
INL	Integral nonlinearity error, over full input range		±1.5	±3.0	LSB
DNL	Differential nonlinearity error, over full input range		±0.8	+2.0/–1.0 ⁽¹⁴⁾	LSB
E_O	Offset error		±1.0	±3.0	LSB
E_G	Gain error ⁽¹⁵⁾		±2.0	±3.0	LSB
E_T	Total unadjusted error, over full input range ⁽¹⁶⁾		±2.5	±4.0	LSB
System performance when using internal reference
N	Resolution		12		bits
INL	Integral nonlinearity error, over full input range		±1.5	±3.0	LSB
DNL	Differential nonlinearity error, over full input range		±0.8	+2.0/–1.0 ⁽¹⁴⁾	LSB
E_O	Offset error		±5.0	±15.0	LSB
E_G	Gain error ⁽¹⁵⁾		±10.0	±30.0	LSB
E_T	Total unadjusted error, over full input range ⁽¹⁶⁾		±10.0	±30.0	LSB
Dynamic characteristics ⁽¹²⁾ ⁽¹⁷⁾
SNR_D	Signal-to-noise-ratio, Differential input, V_ADCIN: –20 dB FS, 1 kHz ⁽¹⁸⁾	70	72		dB
SDR_D	Signal-to-distortion ratio, Differential input, V_ADCIN: –3 dB FS, 1 kHz ⁽¹⁸⁾ ⁽¹⁹⁾ ⁽²⁰⁾	72	75		dB
SNDR_D	Signal-to-Noise+Distortion ratio, Differential input, V_ADCIN: –3 dB FS, 1 kHz ⁽¹⁸⁾ ⁽²¹⁾ ⁽²²⁾	68	70		dB
SNR_S	Signal-to-noise-ratio, Single-ended input, V_ADCIN: –20 dB FS, 1 kHz ⁽²³⁾	60	65		dB
SDR_S	Signal-to-distortion ratio, Single-ended input, V_ADCIN: –3 dB FS, 1 kHz ⁽¹⁹⁾ ⁽²⁰⁾	70	72		dB
SNDR_S	Signal-to-Noise+Distortion ratio, Single-ended input, V_ADCIN: –3 dB FS, 1 kHz ⁽²³⁾ ⁽²¹⁾ ⁽²²⁾	60	63		dB
Temperature sensor
V_TSENS	Temperature sensor voltage, junction temperature 25°C		1.633		V
S_TSENS	Temperature sensor slope at: –40°C to 105°C ambient (extended temperature part)		–13.3		mV/°C
E_TSENS	Temperature sensor accuracy ⁽²⁴⁾ at: –40°C to 105°C ambient (extended temperature part)			±5	°C

(1) Best design practices suggest placing static or quiet digital I/O signals adjacent to sensitive analog inputs to reduce capacitive coupling and crosstalk. Unexpected results can occur if a switching digital I/O is placed adjacent to an ADC input channel or voltage reference input. In addition, analog signals that are adjacent to ADC input channels or reference inputs must meet the R_ADC equivalent input resistance given in this table and must be band-limited to 100 kHz or lower.

(2) Two capacitors in parallel. These capacitors should be as close to the die as possible.

(3) Assumes external filtering network between VREFA+ and VREFA- as shown in Figure 5-26. External reference noise level must be under 12-bit (–74 dB) full-scale input, over input bandwidth, measured at VREFA+ – VREFA-.

(4) Internal reference is connected directly between V_DDA and GNDA (VREFi = V_DDA – GNDA). In this mode, E_O, E_G, E_T, and dynamic specifications are adversely affected due to internal voltage drop and noise on V_DDA and GNDA. Internal reference voltage is selected when VREF field in the ADCCTL register is 0x0.

(5) V_ADCIN = V_INP – V_INN

(6) With signal common-mode voltage as V_DDA / 2.

(7) With signal common-mode voltage as (V_REF+ + V_REF–) / 2.

(8) This parameter is defined as the average of the differential inputs.

(9) As shown in Figure 5-27, R_ADC is the total equivalent resistance in the input line all the way up to the sampling node at the input of the ADC.

(10) See Table 5-14 for full ADC clock frequency specification.

(11) ADC conversion time (t_C) includes the ADC sample time (t_S).

(12) A low-noise environment is assumed to obtain values close to specifications. The board must have good ground isolation between analog and digital grounds and a clean reference voltage. The input signal must be band-limited to Nyquist bandwidth. No antialiasing filter is provided internally.

(13) ADC static measurements taken by averaging over several samples. At least 20-sample averaging is assumed to obtain expected typical or maximum specification values.

(14) 12-bit DNL

(15) Gain error is measured at maximum code after compensating for offset. Gain error is equivalent to the full-scale error. It can be given in % of slope error, or in LSB, as done here.

(16) Total unadjusted error is the maximum error at any one code versus the ideal ADC curve. It includes all other errors (offset error, gain error and INL) at any given ADC code.

(17) ADC dynamic characteristics are measured using low-noise board design, with low-noise reference voltage (< –74-dB noise level in signal bandwidth) and low-noise analog supply voltage. Board noise and ground bouncing couple into the ADC and affect dynamic characteristics. A clean external reference must be used to achieve the listed specifications.

(18) Differential signal with correct common-mode voltage, applied between two ADC inputs.

(19) SDR = –THD in dB.

(20) For higher-frequency inputs, expect degradation in SDR.

(21) SNDR = S/(N+D) = SINAD (in dB)

(22) Effective number of bits (ENOB) can be calculated from SNDR: ENOB = (SNDR – 1.76) / 6.02.

(23) Single-ended inputs are more sensitive to board and trace noise than differential inputs; SNR and SNDR measurements on single-ended inputs are highly dependent on how clean the test setup is. If the input signal is not well isolated on the board, higher noise than specified could be seen at the ADC output.

(24) This parameter does not include ADC error.

Table 5-34 lists the electrical characteristics for the ADC at 2 Msps.

Table 5-34 Electrical Characteristics for ADC at 2 Msps

V_REF+ = 3.3 V, f_ADC = 32 MHz, over operating free-air temperature (unless otherwise noted) (see Figure 5-26 and Figure 5-27)⁽¹⁾

PARAMETER		MIN	TYP	MAX	UNIT
Power supply requirements
V_DDA	ADC supply voltage	2.97	3.3	3.63	V
GNDA	ADC ground voltage		0		V
VDDA and GNDA voltage reference
C_REF	Voltage reference decoupling capacitance		1.0 // 0.01 ⁽²⁾		µF
External voltage reference input
V_REFA+	Positive external voltage reference for ADC, when VREF field in the ADCCTL register is 0x1⁽³⁾	2.4	V_DDA	V_DDA	V
V_REFA-	Negative external voltage reference for ADC, when VREF field in the ADCCTL register is 0x1 ⁽³⁾	GNDA	GNDA	0.3	V
I_VREF	Current on VREF+ input, using external V_REF+ = 3.3 V		330.5	440	µA
I_LVREF	DC leakage current on VREF+ input when external VREF disabled			2.0	µA
C_REF	External reference decoupling capacitance ⁽³⁾		1.0 // 0.01 ⁽²⁾		µF
Analog input
V_ADCIN	Single-ended, full-scale analog input voltage, internal reference⁽⁴⁾⁽⁵⁾	0		V_DDA	V
	Differential, full-scale analog input voltage, internal reference ⁽⁴⁾⁽⁶⁾	–V_DDA		V_VDDA
	Single-ended, full-scale analog input voltage, external reference ⁽³⁾ ⁽⁵⁾	V_REFA-		V_REFA+
	Differential, full-scale analog input voltage, external reference ⁽³⁾⁽⁷⁾	–(V_REFA+ – V_REFA-)		V_REFA+ – V_REFA-
VIN_CM	Input common-mode voltage, differential mode ⁽⁸⁾			[(V_REFA+ + V_REFA-) / 2] ±0.025	V
I_L	ADC input leakage current⁽⁹⁾			2.0	µA
R_ADC	ADC equivalent input resistance ⁽⁹⁾			2.5	kΩ
C_ADC	ADC equivalent input capacitance ⁽⁹⁾			10	pF
R_S	Analog source resistance ⁽⁹⁾			250	Ω
Sampling dynamics
f_ADC	ADC conversion clock frequency⁽¹⁰⁾		32		MHz
f_CONV	ADC conversion rate			2	Msps
t_S	ADC sample time		125		ns
t_C	ADC conversion time ⁽¹¹⁾		0.5		µs
t_LT	Latency from trigger to start of conversion		2		ADC clock cycles
System performance when using external reference ⁽¹²⁾ ⁽¹³⁾
N	Resolution		12		bits
INL	Integral nonlinearity error, over full input range		±1.5	±3.0	LSB
DNL	Differential nonlinearity error, over full input range		±0.8	+2.0/–1.0 ⁽¹⁴⁾	LSB
E_O	Offset error		±1.0	±3.0	LSB
E_G	Gain error ⁽¹⁵⁾		±2.0	±3.0	LSB
E_T	Total unadjusted error, over full input range ⁽¹⁶⁾		±2.5	±4.0	LSB
System performance when using internal reference
N	Resolution		12		bits
INL	Integral nonlinearity error, over full input range		±1.5	±3.0	LSB
DNL	Differential nonlinearity error, over full input range		±0.8	+2.0/–1.0 ⁽¹⁴⁾	LSB
E_O	Offset error		±5.0	±15.0	LSB
E_G	Gain error ⁽¹⁵⁾		±10.0	±30.0	LSB
E_T	Total unadjusted error, over full input range ⁽¹⁶⁾		±10.0	±30.0	LSB
Dynamic characteristics ⁽¹⁷⁾ ⁽¹⁸⁾
SNR_D	Signal-to-noise-ratio, differential input, V_ADCIN: –20 dB FS, 1 kHz ⁽¹⁹⁾	68	72		dB
SDR_D	Signal-to-distortion ratio, differential input, V_ADCIN: –3 dB FS, 1 kHz ⁽¹⁹⁾ ⁽²⁰⁾ ⁽²¹⁾	70	75		dB
SNDR_D	Signal-to-noise+distortion ratio, differential input, V_ADCIN: –3 dB FS, 1 kHz ⁽¹⁹⁾ ⁽²²⁾ ⁽²³⁾	65	70		dB
SNR_S	Signal-to-noise-ratio, single-ended input, V_ADCIN: –20 dB FS, 1 kHz ⁽²⁴⁾	58	65		dB
SDR_S	Signal-to-distortion ratio, single-ended input, V_ADCIN: –3 dB FS, 1 kHz ⁽²⁰⁾ ⁽²¹⁾	68	72		dB
SNDR_S	Signal-to-noise+distortion ratio, single-ended input, V_ADCIN: –3 dB FS, 1 kHz ⁽²⁴⁾ ⁽²²⁾ ⁽²³⁾	58	63		dB

(1) Best design practices suggest placing static or quiet digital I/O signals adjacent to sensitive analog inputs to reduce capacitive coupling and crosstalk. Unexpected results can occur if a switching digital I/O is placed adjacent to an ADC input channel or voltage reference input. In addition, analog signals configured adjacent to ADC input channels or reference inputs must meet the R_ADC equivalent input resistance given in this table and must be band-limited to 100 kHz or lower.

(2) Two capacitors in parallel. These capacitors should be as close to the die as possible.

(3) Assumes external filtering network between VREFA+ and VREFA- as shown in Figure 5-26. External reference noise level must be under 12-bit (–74-dB) full scale input, over input bandwidth, measured at VREFA+ – VREFA-.

(4) Internal reference is connected directly between V_DDA and V_GNDA (V_REFi = V_DDA – V_GNDA). In this mode, E_O, E_G, E_T, and dynamic specifications are adversely affected due to internal voltage drop and noise on V_DDA and GNDA. Internal reference voltage is selected when VREF field in the ADCCTL register is 0x0.

(5) V_ADCIN = V_INP – V_INN

(6) With signal common-mode voltage as V_DDA / 2.

(7) With signal common-mode voltage as (V_REF+ + V_REF-) / 2.

(8) This parameter is defined as the average of the differential inputs.

(9) As shown in Figure 5-27, R_ADC is the total equivalent resistance in the input line all the way up to the sampling node at the input of the ADC.

(10) See Table 5-14 for full ADC clock frequency specification.

(11) ADC conversion time (t_C) includes the ADC sample time (t_S).

(12) A low-noise environment is assumed to obtain values close to specifications. The board must have good ground isolation between analog and digital grounds, a clean reference voltage is assumed, and input signal must be bandlimited to Nyquist bandwidth. No antialiasing filter is provided internally.

(13) ADC static measurements taken by averaging over several samples. At least 20-sample averaging is assumed to obtain expected typical or maximum specification values.

(14) 12-bit DNL

(15) Gain error is measured at maximum code after compensating for offset. Gain error is equivalent to"Full Scale Error." It can be given in % of slope error, or in LSB, as done here.

(16) Total Unadjusted Error is the maximum error at any one code versus the ideal ADC curve. It includes all other errors (offset error, gain error and INL) at any given ADC code.

(17) A low noise environment is assumed to obtain values close to spec. The board must have good ground isolation between analog and digital grounds and a clean reference voltage. The input signal must be band-limited to Nyquist bandwidth. No antialiasing filter is provided internally.

(18) ADC dynamic characteristics are measured using low-noise board design, with low-noise reference voltage (< –74 dB noise level in signal BW) and low-noise analog supply voltage. Board noise and ground bouncing couple into the ADC and affect dynamic characteristics. Clean external reference must be used to achieve the listed specifications.

(19) Differential signal with correct common-mode voltage, applied between two ADC inputs.

(20) SDR = –THD in dB.

(21) For higher-frequency inputs, expect degradation in SDR.

(22) SNDR = S/(N+D) = SINAD (in dB)

(23) Effective number of bits (ENOB) can be calculated from SNDR: ENOB = (SNDR – 1.76) / 6.02.

(24) Single-ended inputs are more sensitive to board and trace noise than differential inputs; SNR and SNDR measurements on single-ended inputs are highly dependent on how clean the test setup is. If the input signal is not well isolated on the board, higher noise than specified could be seen at the ADC output.

Figure 5-26 ADC External Reference Filtering

Figure 5-27 ADC Input Equivalency

5.15.12 Synchronous Serial Interface (SSI)

Table 5-35 SSI Characteristics

over operating free-air temperature (unless otherwise noted) (see Figure 5-28, Figure 5-29, and Figure 5-30)

NO.	PARAMETER			MIN	MAX	UNIT
S1	t_{CLK_PER}	SSIClk cycle time	As master⁽¹⁾	16.67		ns
S1	t_{CLK_PER}	SSIClk cycle time	As slave⁽²⁾	100		ns
S2	t_{CLK_HIGH}	SSIClk high time	As master	8.33		ns
S2	t_{CLK_HIGH}	SSIClk high time	As slave	50		ns
S3	t_{CLK_LOW}	SSIClk low time	As master	8.33		ns
S3	t_{CLK_LOW}	SSIClk low time	As slave	50		ns
S4	t_CLKR	SSIClk rise time⁽³⁾		1.25		ns
S5	t_CLKF	SSIClk fall time ⁽³⁾		1.25		ns
S6	t_TXDMOV	Master mode: master Tx data output (to slave) valid time from edge of SSIClk			4.00	ns
S7	t_TXDMOH	Master mode: master Tx data output (to slave) hold time after next SSIClk		0.60		ns
S8	t_RXDMS	Master mode: master Rx data In (from slave) setup time		7.89		ns
S9	t_RXDMH	Master mode: master Rx data In (from slave) hold time		0		ns
S10	t_TXDSOV	Slave mode: master Tx data output (to master) valid time from edge of SSIClk			47.60⁽⁴⁾	ns
S11	t_TXDSOH	Slave mode: slave Tx data output (to master) hold time from next SSIClk		37.4⁽⁵⁾		ns
S13	t_RXDSSU	Slave mode: Rx data in (from master) setup time		0		ns
S14	t_RXDSH	Slave mode: Rx data in (from master) hold time		37.03⁽⁶⁾		ns

(1) In master mode, the system clock must be at least twice as fast as the SSIClk.

(2) In slave mode, the system clock must be at least 12 times faster than the SSIClk.

(3) The delays shown are using 12-mA drive strength.

(4) This MAX value is for the minimum slave mode t_SYSCLK period (8.33 ns). To find the MAX t_TXDSOV value for a larger t_SYSCLK, use the equation: 4 × t_SYSCLK + 14.25.

(5) This MIN value is for the minimum slave mode t_SYSCLK (8.33 ns). To find the MIN t_TXDSOH value for a larger t_SYSCLK, use the equation: 4 × t_SYSCLK + 4.08.

(6) This MIN value is for the minimum slave mode t_SYSCLK (8.33 ns). To find the MIN t_TXDSH value for a larger t_SYSCLK, use the equation: 4 × t_SYSCLK + 3.70.

MSP432E411Y LMI-SSI-Timing_ti_blizzard.gif

Figure 5-28 SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement

MSP432E411Y SSI_Timing_SPI_blizzard-master.gif

Figure 5-29 Master Mode SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1

MSP432E411Y SSI_Timing_SPI_blizzard-slave.gif

Figure 5-30 Slave Mode SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1

Table 5-36 lists the characteristics for Bi-SSI and Quad-SSI.

Table 5-36 Bi- and Quad-SSI Characteristics⁽¹⁾

over operating free-air temperature (unless otherwise noted)

NO.	PARAMETER		MIN	MAX	UNIT
S15	t_{CLK_PER}	SSIClk cycle time, as master ⁽²⁾	16.67		ns
S16	t_{CLK_HIGH}	SSIClk high time, as master	8.33		ns
S17	t_{CLK_LOW}	SSIClk low time, as master	8.33		ns
S18	t_CLKR	SSIClk rise time ⁽³⁾	1.25		ns
S19	t_CLKF	SSIClk fall time ⁽³⁾	1.25		ns
S20	t_TXDMOV	Master mode: master SSInXDATn data output (to slave) valid time from edge of SSIClk		4.04	ns
S21	t_TXDMOH	Master mode: master SSInXDATn data output (to slave) hold time after next SSIClk	0.60		ns
S22	t_RXDMS	Master mode: master SSInXDATn data in (from slave) setup time	5.78		ns
S23	t_RXDMH	Master mode: master SSInXDATn data in (from slave) hold time	0		ns

(1) Parameters S15 to S23 correspond to parameters S1 to S9 in Figure 5-28 and Figure 5-29.

(2) In master mode, the system clock must be at least twice as fast as the SSIClk.

(3) The delays shown are using 12-mA drive strength.

5.15.13 Inter-Integrated Circuit (I²C) Interface

Table 5-37 lists the characteristics for the I²C interface.

Table 5-37 I²C Characteristics

over operating free-air temperature (unless otherwise noted) (see Figure 5-31)

NO.	PARAMETER			MIN	TYP	MAX	UNIT
I1⁽¹⁾	t_SCH	Start condition hold time		36			system clock cycles
I2 ⁽¹⁾	t_LP	Clock low period		36			system clock cycles
I3 ⁽²⁾	t_SRT	I2CSCL and I2CSDA rise time (V_IL = 0.5 V to V_IH = 2.4 V)				See ⁽²⁾	ns
I4	t_DH	Data hold time	Slave		2		system clock cycles
I4	t_DH	Data hold time	Master		7		system clock cycles
I5 ⁽³⁾	t_SFT	I2CSCL and I2CSDA fall time (V_IH = 2.4 V to V_IL = 0.5 V)			9	10	ns
I6 ⁽¹⁾	t_HT	Clock high time		24			system clock cycles
I7	t_DS	Data setup time		18			system clock cycles
I8 ⁽¹⁾	t_SCSR	Start condition setup time (for repeated start condition only)		36			system clock cycles
I9 ⁽¹⁾	t_SCS	Stop condition setup time		24			system clock cycles
I10	t_DV	Data valid	Slave		2		system clock cycles
I10	t_DV	Data valid	Master		(6 × (1 + TPR)) + 1		system clock cycles

(1) Values depend on the value programmed into the TPR bit in the I²C Master Timer Period (I2CMTPR) register; a TPR programmed for the maximum I2CSCL frequency (TPR = 0x2) results in a minimum output timing listed in this table. The I²C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL low period. The actual position is affected by the value programmed into the TPR; however, the values in this table are minimum values.

(2) Because I2CSCL and I2CSDA operate as open-drain-type signals, which the controller can only actively drive low, the time I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pullup resistor values.

(3) Specified at a nominal 50-pF load

Figure 5-31 I²C Timing

5.15.14 Ethernet Controller

5.15.14.1 DC Characteristics

The parameters listed in Table 5-38, with the exception of R_BIAS, apply to transmit pins of the Ethernet PHY, which are generally the EN0TXOP and EN0TXON signals during standard operation but can also be the EN0RXIN and EN0RXIP signals if Auto-MDIX is enabled.

Table 5-38 Ethernet PHY DC Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER		MIN	TYP	MAX	UNIT
R_BIAS	Value of the pulldown resistor on the RBIAS pin	4.82	4.87	4.92	kΩ
V_{TPTD_100}	100M transmit voltage	0.95	1	1.05	V
V_TPTDSYM	100M transmit voltage symmetry	–2%		2%
V_OVRSHT	Output overshoot			5%
V_{TPTD_10}	10M transmit voltage	2.2	2.5	2.8	V
V_TH1	10Base-T Receive threshold		200		mV

5.15.14.2 Clock Characteristics for Ethernet

Table 5-39 lists the specifications of the MOSC 25-MHz crystal.

Table 5-39 MOSC 25-MHz Crystal Specification⁽¹⁾

over operating free-air temperature (unless otherwise noted) (see Figure 5-32)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
N1	f_MOSC25	Frequency		25		MHz
	f_TOL	Frequency tolerance at operational temperature	0		±50	ppm
	f_STA	Frequency stability at 1-year aging			±5	ppm

(1) See Table 5-12 for additional MOSC requirements.

Figure 5-32 MOSC Crystal Characteristics for Ethernet

Table 5-40 lists the specifications of the single-ended 25-MHz oscillator.

Table 5-40 MOSC Single-Ended 25-MHz Oscillator Specification ⁽¹⁾

over operating free-air temperature (unless otherwise noted) (see Figure 5-33)

NO.	PARAMETER			MIN	TYP	MAX	UNIT
N4	f_OSC	Frequency			25		MHz
	f_TOL	Frequency tolerance at operational temperature		0		±50	ppm
	t_STA	Frequency stability at 1-year aging				±50	ppm
N5	t_RF	Frequency rise and fall time				1	ns
	t_J	Jitter	Cycle to cycle		50		ps
	t_J	Jitter	Over 10 ms			1	ns
	DC	Duty cycle		40%		60%

MSP432E411Y Ethernet_Oscillator_Specs.gif

Figure 5-33 Single-Ended MOSC Characteristics for Ethernet

Table 5-41 lists the specifications of the EN0RREF_CLK 50-MHz oscillator.

Table 5-41 EN0RREF_CLK 50-MHz Oscillator Specification

over operating free-air temperature (unless otherwise noted) (see Figure 5-34)

NO.	PARAMETER			MIN	TYP	MAX	UNIT
N8	f_OSC	Frequency			50		MHz
	f_TOL	Frequency tolerance at operational temperature		0		±50	ppm
	t_STA	Frequency stability at 1-year aging				±50	ppm
N9	t_RF	Frequency rise and fall time				1.5	ns
	t_J	Jitter	Cycle to cycle		50		ps
	t_J	Jitter	Over 10 ms			1	ns
	DC	Duty cycle		40%		60%

MSP432E411Y Ethernet_EN0REFCLK_Specs.gif

Figure 5-34 EN0RREF_CLK 50-MHz Oscillator Characteristics

5.15.14.3 AC Characteristics

Table 5-42 lists the timing characterists of the enable and reset.

Table 5-42 Ethernet Controller Enable and Software Reset Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-35)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
N16	t_EN	Time from the System Control enable of the PHY to energy on the PMD output pin ⁽¹⁾ ⁽²⁾	45			µs
N17	t_SWRST	Time from software reset of the PHY to energy on the PMD output pin	110			ns

(1) The PHY is enabled through System Control by setting the P0 bit in the PCEPHY register and the R0 bit in the RCGCPHY register.

(2) This minimum timing assumes the PHYHOLD bit in the EMACPC register is not set.

Figure 5-35 Reset Timing

Table 5-43 lists the MII serial management timing.

Table 5-43 MII Serial Management Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-36)

NO.	PARAMETER		MIN	MAX	UNIT
N20	f_MDC	EN0MDC frequency		2.5	MHz
N21	t_{MDIO_DLY}	EN0MDC to EN0MDIO (output) delay time	0	See ⁽¹⁾	ns
N22	t_{MDIO_SU}	EN0MDIO (input) to EN0MDC setup time	10		ns
N23	t_{MDIO_HLD}	EN0MDIO (input) to EN0MDC hold time	10		ns

(1) [1 / (2 × f_MDC)] + 1 system clock period + 10 ns

MSP432E411Y Ethernet_MII_Serial_Mgmt.gif

Figure 5-36 Station Management Write and Read Timing

Table 5-44 lists the 100-Mbps MII transmit timing.

Table 5-44 100-Mbps MII Transmit Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-37)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
N26	t_{TXCK_HI}	EN0TXCK high time	16	20	24	ns
N27	t_{TXCK_LO}	EN0TXCK low time	16	20	24	ns
N28	t_{TX_DLY}	EN0TXCK to EN0TXDn, EN0TXEN delay	0		25	ns

Figure 5-37 100-Mbps MII Transmit Timing

Table 5-45 lists the 100-Mbps MII receive timing.

Table 5-45 100-Mbps MII Receive Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-38)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
N30	t_{RXCK_HI}	EN0RXCK high time	16	20	24	ns
N31	t_{RXCK_LO}	EN0RXCK low time	16	20	24	ns
N32	t_{RXCK_SU}	EN0RXDn, EN0RXDV, EN0RXER data setup to EN0RXCK	10			ns
N33	t_{RXCK_HLD}	EN0RXDn, EN0RXDV, EN0RXER data hold to EN0RXCK	0			ns

Figure 5-38 100-Mbps MII Receive Timing

Table 5-46 lists the 100Base-TX transmit timing.

Table 5-46 100Base-TX Transmit Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-39)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
N38	t_RF	100-Mbps PMD output pair t_R and t_F ⁽¹⁾	3	4	5	ns
N38	t_{RF_MM}	100-Mbps t_R and t_F symmetry ⁽²⁾ ⁽³⁾			500	ps
N39	t_{RF_JTTR}	100-Mbps PMD output pair transmit jitter			1.4	ns

(1) Rise and fall times taken at 10% and 90% of the +1 or –1 amplitude.

(2) Normal mismatch is the difference between the maximum and minimum of all rise and fall times

(3) Choice of Ethernet transformer magnetics can affect this parameter.

MSP432E411Y Ethernet_100Base-T_TX_RF_Jitter.gif

Figure 5-39 100 Base-TX Transmit Timing

Table 5-47 lists the 10-Mbps MII transmit timing.

Table 5-47 10-Mbps MII Transmit Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-40)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
N45	t_{TXCK_HI}	EN0TXCK high time	190	200	210	ns
N46	t_{TXCK_LO}	EN0TXCK low time	190	200	210	ns
N47	t_{TX_DLY}	EN0TXCK to EN0TXDn, EN0TXEN delay	0		25	ns

Figure 5-40 10-Mbps MII Transmit Timing

Table 5-48 lists the 10-Mbps MII receive timing.

Table 5-48 10-Mbps MII Receive Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-41)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
N50	t_{RXCK_HI}	EN0RXCK high time	160	200	240	ns
N51	t_{RXCK_LO}	EN0RXCK low time	160	200	240	ns
N52	t_{RX_SU}	EN0RXCK to EN0RXDn, EN0RXDV, EN0RXER setup	100			ns
N53	t_{RX_HLD}	EN0RXCK to EN0RXDn, EN0RXDV, EN0RXER hold	100			ns

Figure 5-41 10-Mbps MII Receive Timing

Table 5-49 lists the 10Base-T normal link pulse timing.

Table 5-49 10Base-T Normal Link Pulse Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-42)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
N69	t_{LP_PER}	Link pulse period		76		ms
N70	t_{LP_WID}	Link pulse width		100		µs

MSP432E411Y Ethernet_10BaseT_Link_Pulse.gif

Figure 5-42 10Base-TX Normal Link Pulse Timing

Table 5-50 lists the Auto-Negotiation FLP timing.

Table 5-50 Auto-Negotiation Fast Link Pulse (FLP) Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-43)

NO.	PARAMETER		TYP	UNIT
N72	t_CLKP	Clock pulse to clock pulse period	125	µs
N73	t_CLKDP	Clock pulse to data pulse period	62	µs
N74	t_PUL	Clock, data pulse width	110	ns
N75	t_BRSTP	FLP burst to flp burst period	16	ms
N76	t_BRSTW	Burst width	2	ms

MSP432E411Y Ethernet_Auto_Neg_Fast_Link_Pulse.gif

Figure 5-43 Auto-Negotiation Fast Link Pulse Timing

Table 5-51 lists the 100Base-TX signal detect timing.

Table 5-51 100Base-TX Signal Detect Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-44)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
N79	t_ON	SD internal turnon time			100	µs
N80	t_OFF	Internal turnoff time			200	µs

MSP432E411Y Ethernet_10BaseT_Signal_Detect.gif

Figure 5-44 100Base-TX Signal Detect Timing

Table 5-52 lists the RMII transmit timing.

Table 5-52 RMII Transmit Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-45)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
N86	f_REFCLK	EN0RREF_CLK frequency		50		MHz
	DC_REFCLK	EN0RREF_CLK duty cycle	40%		60%
N87	t_{TX_DLY}	EN0RREF_CLK to EN0TXDn, EN0TXEN delay	2		14	ns

Figure 5-45 RMII Transmit Timing

Table 5-53 lists the RMII receive timing.

Table 5-53 RMII Receive Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-46)

NO.	PARAMETER		MIN	TYP	MAX	UNIT
N91	f_REFCLK	EN0RREF_CLK frequency		50		MHz
	DC_REFCLK	EN0RREF_CLK duty cycle	40%		60%
N92	t_{RX_SU}	EN0RXDn, EN0RXEN, EN0CRS setup time to EN0RREF_CLK	4			ns
N93	t_{RX_HLD}	EN0RXDn, EN0RXEN, EN0CRS hold time from EN0RREF_CLK	2			ns

Figure 5-46 RMII Receive Timing

5.15.15 Universal Serial Bus (USB) Controller

The USB controller electrical specifications are compliant with the Universal Serial Bus Specification Rev 2.0 (full-speed and low-speed support) and the On-The-Go Supplement to the USB 2.0 Specification Rev 1.0. Some components of the USB system are integrated within the microcontroller and specific to the microcontroller design.

NOTE

GPIO pin PB1, which can be configured as the USB0VBUS signal, is the only pin that is 5-V tolerant on the device.

Table 5-54 lists the timing characteristics of the ULPI interface.

Table 5-54 ULPI Interface Timing

over operating free-air temperature (unless otherwise noted) (see Figure 5-47)

NO.	PARAMETER		MIN	MAX	UNIT
Timings with respect to external clock source input to USB0CLK
U1	t_SUC	Setup time (control in) USB0DIR, USB0NXT	4.8		ns
U2	t_SUD	Setup time (data in) USB0Dn	3.5		ns
U3	t_HTC	Hold time (control in) USB0DIR, USB0NXT	0		ns
U4	t_HTD	Hold time (data in) USB0Dn	0		ns
U5	t_ODC	Output delay (control out) USB0STP	3.7	9.5	ns
U6	t_ODD	Output delay (data out) USB0Dn	3.7	9.5	ns
Timings with USB0CLK as clock output
U1	t_SUC	Setup time (control in) USB0DIR, USB0NXT	6.0		ns
U2	t_SUD	Setup time (data in) USB0Dn	4.6		ns
U3	t_HTC	Hold time (control in) USB0DIR, USB0NXT	0		ns
U4	t_HTD	Hold time (data in) USB0Dn	0		ns
U5	t_ODC	Output delay (control out) USB0STP	4.0	10.6	ns
U6	t_ODD	Output delay (data out) USB0Dn	4.0	10.6	ns

Figure 5-47 ULPI Interface Timing Diagram

5.15.16 LCD Controller

The LCD controller consists of two independent controllers, the raster controller and the LCD interface display driver (LIDD) controller. Each controller operates independently from the other and only one of them is active at any given time.

The LIDD controller supports an asynchronous LCD interface that provides full timing programmability of control signals (CS, WE, OE, ALE) and output data. The LIDD controller also supports synchronous interface in Motorola 6800 mode and Intel 8080 mode through the use of the external LCDMCLK output.
The raster controller supports the synchronous LCD interface and provides timing and data for constant graphics refresh to a passive display. The raster controller supports a variety of monochrome and full-color display types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale and serializer. Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block in the system. The µDMA supplies the graphics data to the raster engine which, in turn, outputs to the external LCD device.

The maximum resolution for the LCD controller is 2048 × 2048 pixels. The maximum frame rate is determined by the image size in combination with the pixel clock rate.

The LCD signals must be configured with a drive strength of 8 mA with slew rate control.

Table 5-55 lists the load capacitance limits of the LCD controller.

Table 5-55 LCD Controller Load Capacitance Limits

over operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
C_LOAD	LCD output load capacitance	LIDD mode	5		50	pF
C_LOAD	LCD output load capacitance	Raster mode	3		30	pF

NOTE

A 25-pF load is assumed for LCD timings.

5.15.16.1 LCD Interface Display Driver (LIDD Mode)

In LIDD mode, the LIDDCS0CFG register allows for full programmability of the read and write strobes, data and enables. In the LCDCS0CFG register, the following parameters can be configured with respect to the internal MCLK:

WRSU (bits[31:27]): Number of MCLK cycles that the LCDDATA bus, output enable, ADE, DIR, and CS0 signals must be ready before the write strobe. The minimum value is 0x0.
WRDUR (bits[26:21]): Number of MCLK cycles for which the write strobe is held active when performing a write access. The minimum value is 0x1.
WRHOLD (bits[20:17]): Number of MCLK cycles for which the LCDDATA bus, output enable, ALE, DIR, and CS0 signals are held after the write strobe is deasserted when performing a write access. The minimum value is 0x1.
RDSU (bits[16:12]): When performing a read access, this field defines the number of MCLK cycles that the LCDDATA bus, output enable, ALE, DIR, and CS0 signals must be ready before the read strobe is asserted.
RDDUR (bits[11:6]): Number of MCLK cycles for which the read strobe is held active when performing a read access. The minimum value is 0x1.
RDHOLD (bits[5:2]): Number of MCLK cycles for which the LCDDATA bus, output enable, ALE, DIR, and CS0 signals are held after the read strobe is deasserted when performing a read access. The minimum value is 0x1.
GAP (bits[1:0]): Number of MCLK cycles (GAP + 1) between the end of one CS0 device access and the start of another CS0 device access, unless both accesses are reads. In this case, this delay is not incurred. The minimum value is 0x0.

Essentially, output valid/hold and input setup/hold times in LIDD mode are programmed by these fields. In addition, the inherent clock delay from the internal MCLK transition to the signal output adds or subtracts to these programmed times as indicated in the following tables and figures.

Table 5-56 lists the LCD switching characteristics.

Table 5-56 LCD Switching Characteristics

over operating free-air temperature (unless otherwise noted) (see Figure 5-48, Figure 5-49, Figure 5-50, and Figure 5-51)

NO.	PARAMETER		TYP	MAX	UNIT
L1	t_CYC	Internal MCLK cycle time	50		ns
L2	t_CYCH	Internal MCLK pulse duration high	25		ns
L3	t_CYCL	Internal MCLK pulse duration low	25		ns
L4	t_DLYVAL	Delay time from internal MCLK high to LCDDATA[15:0] valid (write)		11.6	ns
L5	t_DLYINV	Delay time from internal MCLK high to LCDDATA[15:0] invalid (write)		4.0	ns
L6	t_DLYHAC	Delay time, internal MCLK high to LCDAC		11.19	ns
L7	t_TRANAC	LCDAC transition time		5.9	ns
L8	t_DLYFP	Delay time from internal MCLK high to LCDFP		10.5	ns
L9	t_TRANFP	LCDFP transition time		5.9	ns
L10	t_DLYLP	Delay time internal MCLK high to LCDLP		11.0	ns
L11	t_TRANLP	LCDLP transition time		5.9	ns
L12	t_DLYCP	Delay time of internal MCLK to LCDCP		8.4	ns
L13	t_TRANCP	LCDCP transition time		5.9	ns
L14	t_DLYDZ	Delay time from internal MCLK high to LCDDATA[15:0] Hi-Z (read cycle)		11.7	ns
L15	t_DLYDD	Delay time from internal MCLK high to LCDDATA[15:0] active (read cycle)		11.0	ns
L19	t_TRANMCLK	Internal MCLK transition time		5.9	ns
L20	t_TRANPKT	LCDDATA transition time from one data packet to next		5.9	ns

Table 5-57 lists the timing requirements for LCDDATA in LIDD mode.

Table 5-57 Timing Requirements for LCDDATA in LIDD Mode

over operating free-air temperature (unless otherwise noted) (see Figure 5-48, Figure 5-49, Figure 5-50, and Figure 5-51)

NO.	PARAMETER		MIN	UNIT
L16	t_STDATA	LCDDATA[15:0] setup time (read) before internal MCLK high	20	ns
L17	t_HTDATA	LCDDATA[15:0] hold time (read) after internal MCLK high	0	ns
L18	t_TRANRDATA	LCDDATA read transition time	5.9	ns

5.15.16.1.1 Hitachi Mode

Hitachi mode is an asynchronous mode that does not use an external LCDMCLK and allows for full programmability of the read and write strobes, data, and enables through the LIDDCS0CFG register. In addition to the parameter delays configured in the LIDDCS0CFG register, the delay times in the following figures that are from the internal MCLK to the signal output must be added to the programmed delays for full timing information. All of the parameter values associated with the following figures can be found in Table 5-56 and Table 5-57.

In Figure 5-48, Figure 5-49, and Figure 5-50 the second LCDMCLK is shown as E1 and can be used as the enable strobe for a second display in Hitachi mode. The primary enable strobe is the LCDAC signal.

NOTE

The acronyms WRSU, WRDUR, WRHOLD, and GAP in the following figures correspond to the bit fields of the LIDDCS0CFG register described in Section 5.15.16.1.

Figure 5-48 Command Write in Hitachi Mode

Figure 5-49 Data Write in Hitachi Mode

Figure 5-50 Command Read in Hitachi Mode

Figure 5-51 Data Read in Hitachi Mode

5.15.16.1.2 Motorola 6800 Mode

Motorola 6800 mode can be configured to perform asynchronous operations or synchronous operations. When configured in asynchronous mode, LCDMCLK is not required, so it performs the CS1 function. When configured in synchronous mode, MCLK is available externally through the signal LCDMCLK. In asynchronous mode, the internal MCLK shown represents the internal clock that sequences the other signals. All parameter values associated with the following figures can be found in Table 5-56 and Table 5-57.

NOTE

In asynchronous Motorola 6800 mode, LCDCP functions as the read and write strobe.

NOTE

The acronyms WRSU, WRDUR, WRHOLD, GAP, RDHOLD, RDSU, and RDDUR in Figure 5-52, Figure 5-53, and Figure 5-54 correspond to the bit fields of the LIDDCS0CFG register described in Section 5.15.16.1.

Figure 5-52 Motorola 6800 Graphic Display Mode Write (Synchronous and Asynchronous Operation)

Figure 5-53 Motorola 6800 Graphic Display Mode Read (Synchronous and Asynchronous Operation)

Figure 5-54 Motorola 6800 Graphic Display Mode Status (Synchronous and Asynchronous Operation)

5.15.16.1.3 Intel 8080 Mode

Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in asynchronous mode, LCDMCLK is not required, so it performs the CS1 function. When configured in synchronous mode, MCLK is available externally through the signal LCDMCLK. In asynchronous mode, the internal MCLK shown represents the internal clock that sequences the other signals. All of the parameter values associated with the following figures can be found in Table 5-56 and Table 5-57.

NOTE

The acronyms WRSU, WRDUR, WRHOLD, GAP, RDHOLD, RDSU, and RDDUR in Figure 5-55, Figure 5-56, and Figure 5-57 correspond to the bit fields of the LIDDCS0CFG register described in Section 5.15.16.1.

Figure 5-55 Micro-Interface Graphic Display Intel Write

Figure 5-56 Micro-Interface Graphic Display Intel Read

Figure 5-57 Micro-Interface Graphic Display Intel Status

5.15.16.2 LCD Raster Mode

Table 5-58 lists the LCD raster mode characteristics.

Table 5-58 Switching Characteristics for LCD Raster Mode

over operating free-air temperature (unless otherwise noted) (see Figure 5-58, Figure 5-59, Figure 5-60, Figure 5-61, and Figure 5-62)

NO.	PARAMETER		MIN	MAX	UNIT
L21	t_CYC	LCDCP cycle time	16.67		ns
L22	t_PH	LCDCP pulse width high	8.33		ns
L23	t_PL	LCDCP pulse width low	8.33		ns
L24	t_DLYVAL	Delay time from LCDCP to LCDDATA[23:0] valid (write)	2.0	7.3	ns
L25	t_DLYINV	Delay time from LCDCP to LCDDATA[23:0] invalid (write)	2.0	7.3	ns
L26	t_DLYHAC	Delay time, LCDCP to LCDAC	1.9	7.0	ns
L27	t_TRANAC	LCDAC transition time	0.5	3.3	ns
L28	t_DLYFP	Delay time from LCDCP high to LCDFP	1.7	6.5	ns
L29	t_TRANFP	LCDFP transition time	0.5	3.3	ns
L30	t_DLYLP	Delay time from LCDCP high to LCDLP	2.0	6.8	ns
L31	t_TRANLP	LCDLP transition time	0.5	3.3	ns
L32	t_TRANCP	LCDCP transition time	0.5	3.3	ns
L33	t_TRANDATA	LCDDATA transition time	0.5	3.3	ns

Frame-to-frame timing is derived through the following parameters in the LCD Raster Timing 1 (LCDRASTRTIM1) register:

Vertical front porch (VFP)
Vertical sync pulse width (VSW)
Vertical back porch (VBP)
Lines per panel (MSBLPP + LPP)

Line-to-line timing is derived through the following parameters in the LCD Raster Timing 0 (LCDRASTRTIM0) register:

Horizontal front porch (HFP)
Horizontal sync pulse width (HSW)
Horizontal back porch (HBP)
Pixels per panel (PPLMSB + PPLLSB)

LCDAC timing is derived through the following parameter in the LCD Raster Timing 2 (LCDRASTRTIM2) register:

AC bias frequency (ACBF)

Figure 5-58 shows the display format produced in raster mode. An entire frame is delivered one line at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is denoted by the activation of I/O signal LCDFP (VSYNC). The beginning of each new line is denoted by the activation of I/O signal LCDLP (HSYNC).

Figure 5-58 LCD Raster-Mode Display Format

Figure 5-59 LCD Raster-Mode Active

Figure 5-60 LCD Raster-Mode Passive

Figure 5-61 LCD Raster-Mode Control Signal Activation

Figure 5-62 LCD Raster-Mode Control Signal Deactivation

5.15.17 Analog Comparator

Table 5-59 lists the characteristics of the comparator.

Table 5-59 Analog Comparator Characteristics

over operating free-air temperature (unless otherwise noted) ⁽¹⁾ ⁽²⁾

PARAMETER		MIN	TYP	MAX	UNIT
V_INP, V_INN ⁽³⁾	Input voltage range	GNDA		V_DDA	V
V_CM	Input common-mode voltage range	GNDA		V_DDA	V
V_OS	Input offset voltage		±10	±50 ⁽⁵⁾	mV
I_INP, I_INN	Input leakage current over full voltage range			2.0	µA
C_MRR	Common-mode rejection ratio		50		dB
t_RT	Response time			1.0 ⁽⁴⁾	µs
t_MC	Comparator mode change to output valid			10	µs

(1) Best design practices suggest placing static or quiet digital I/O signals adjacent to sensitive analog inputs to reduce capacitive coupling and crosstalk.

(2) To achieve best analog results, keep the source resistance driving the analog inputs, V_INP and V_INN, low.

(3) The external voltage inputs to the analog comparator are designed to be highly sensitive and can be affected by external noise on the board. For this reason, V_INP and V_INN must be set to different voltage levels during idle states to ensure the analog comparator triggers are not enabled. If an internal voltage reference is used, it should be set to a mid-supply level. When operating in sleep or deep-sleep modes, disable the analog comparator module or set the external voltage inputs to different levels (greater than the input offset voltage) to achieve minimum current draw.

(4) Measured at external V_REF = 100 mV, input signal switching from 75 mV to 125 mV

(5) Measured at V_REF = 100 mV

Table 5-60 lists the characteristics for the comparator.

Table 5-60 Analog Comparator Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER		TYP	MAX	UNIT
R_HR	Resolution in high range	V_DDA / 29.4		V
R_LR	Resolution in low range	V_DDA / 22.12		V
A_HR	Absolute accuracy high range		±R_HR / 2	V
A_LR	Absolute accuracy low range		±R_LR / 2	V

Table 5-61 and Table 5-62 list the reference voltages for the comparator under different conditions.

Table 5-61 Analog Comparator Voltage Reference Characteristics

V_DDA = 3.3 V, EN = 1, RNG = 0, over operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IREF	Reference voltage	VREF = 0x0	0.731	0.786	0.841	V
		VREF = 0x1	0.843	0.898	0.953
		VREF = 0x2	0.955	1.010	1.065
		VREF = 0x3	1.067	1.122	1.178
		VREF = 0x4	1.180	1.235	1.290
		VREF = 0x5	1.292	1.347	1.402
		VREF = 0x6	1.404	1.459	1.514
		VREF = 0x7	1.516	1.571	1.627
		VREF = 0x8	1.629	1.684	1.739
		VREF = 0x9	1.741	1.796	1.851
		VREF = 0xA	1.853	1.908	1.963
		VREF = 0xB	1.965	2.020	2.076
		VREF = 0xC	2.078	2.133	2.188
		VREF = 0xD	2.190	2.245	2.300
		VREF = 0xE	2.302	2.357	2.412
		VREF = 0xF	2.414	2.469	2.525

Table 5-62 Analog Comparator Voltage Reference Characteristics

V_DDA = 3.3 V, EN = 1, RNG = 1, over operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IREF	Reference voltage	VREF = 0x0	0.000	0.000	0.074	V
		VREF = 0x1	0.076	0.149	0.223
		VREF = 0x2	0.225	0.298	0.372
		VREF = 0x3	0.374	0.448	0.521
		VREF = 0x4	0.523	0.597	0.670
		VREF = 0x5	0.672	0.746	0.820
		VREF = 0x6	0.822	0.895	0.969
		VREF = 0x7	0.971	1.044	1.118
		VREF = 0x8	1.120	1.193	1.267
		VREF = 0x9	1.269	1.343	1.416
		VREF = 0xA	1.418	1.492	1.565
		VREF = 0xB	1.567	1.641	1.715
		VREF = 0xC	1.717	1.790	1.864
		VREF = 0xD	1.866	1.939	2.013
		VREF = 0xE	2.015	2.089	2.162
		VREF = 0xF	2.164	2.238	2.311

5.15.18 Pulse-Width Modulator (PWM)

Table 5-63 lists the PWM timing characteristics.

Table 5-63 PWM Timing Characteristics

over operating free-air temperature (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
t_FLTW	Minimum fault pulse width	2		PWM clock periods
t_FLTMAX	MnFAULTn assertion to PWM inactive ⁽¹⁾		24 + (1 PWM clock)	ns
t_FLTMIN	MnFAULTn deassertion to PWM active ⁽²⁾	5		ns

(1) This parameter value can vary depending on the PWM clock frequency which is controlled by the System Clock and a programmable divider field in the PWMCC register.

(2) The latch and minimum fault period functions that can be enabled in the PWMnCTL register can change the timing of this parameter.

5.15.19 Emulation and Debug

Table 5-64 lists the JTAG characteristics.

Table 5-64 JTAG Characteristics

over operating free-air temperature (unless otherwise noted) (see Figure 5-63 and Figure 5-64)

NO.	PARAMETER			MIN	TYP	MAX	UNIT
J1	f_TCK	TCK operational clock frequency		0		10	MHz
J2	t_TCK	TCK operational clock period		100			ns
J3	t_{TCK_LOW}	TCK clock low time			t_TCK / 2		ns
J4	t_{TCK_HIGH}	TCK clock high time			t_TCK / 2		ns
J5	t_{TCK_R}	TCK rise time		0		10	ns
J6	t_{TCK_F}	TCK fall time		0		10	ns
J7	t_{TMS_SU}	TMS setup time to TCK rise		8			ns
J8	t_{TMS_HLD}	TMS hold time from TCK rise		4			ns
J9	t_{TDI_SU}	TDI setup time to TCK rise		18			ns
J10	t_{TDI_HLD}	TDI hold time from TCK rise		4			ns
J11	t_{TDO_ZDV}	TCK fall to data valid from Hi-Z	2-mA drive		13	35	ns
			4-mA drive		9	26
			8-mA drive		8	26
			8-mA drive with slew rate control		10	29
			10-mA drive		11	13
			12-mA drive		11	14
J12	t_{TDO_DV}	TCK fall to data valid from data valid	2-mA drive		14	20	ns
			4-mA drive		10	26
			8-mA drive		8	21
			8-mA drive with slew rate control		10	26
			10-mA drive		12	14
			12-mA drive		12	15
J13	t_{TDO_DVZ}	TCK fall to Hi-Z from data valid	2-mA drive		7	16	ns
			4-mA drive		7	16
			8-mA drive		7	16
			8-mA drive with slew rate control		8	19
			10-mA drive		20	22
			12-mA drive		20	25

Figure 5-63 JTAG Test Clock Input Timing

Figure 5-64 JTAG Test Access Port (TAP) Timing

5 Specifications

5.1 Absolute Maximum Ratings

5.2 ESD Ratings

5.3 Recommended Operating Conditions

5.4 Recommended DC Operating Conditions

5.5 Recommended GPIO Operating Characteristics

5.6 Recommended Fast GPIO Pad Operating Conditions

5.7 Recommended Slow GPIO Pad Operating Conditions

5.8 GPIO Current Restrictions

Table 5-1 Maximum GPIO Package Side Assignments

5.9 I/O Reliability

5.10 Current Consumption

5.11 Peripheral Current Consumption

5.12 LDO Regulator Characteristics

5.13 Power Dissipation

5.14 Thermal Resistance Characteristics, 212-Pin ZAD (NFBGA) Package

5.15 Timing and Switching Characteristics

5.15.1 Load Conditions

Table 5-2 Load Conditions

5.15.2 Power Supply Sequencing

5.15.2.1 Power and Brownout

Table 5-3 Power and Brownout Levels

5.15.2.1.1 VDDA Levels

5.15.2.1.2 VDD Levels

5.15.2.1.3 VDDC Levels

5.15.2.1.4 VDD Glitch Response

5.15.2.1.5 VDD Droop Response

5.15.3 Reset Timing

Table 5-4 Reset Characteristics

5.15.4 Clock Specifications

5.15.4.1 PLL Specifications

Table 5-5 Phase Locked Loop (PLL) Characteristics

5.15.4.1.1 PLL Configuration

Table 5-6 Examples of System Clock Frequencies

Table 5-7 Actual PLL Frequency(1)

5.15.4.2 PIOSC Specifications

Table 5-8 PIOSC Clock Characteristics

5.15.4.3 Low-Frequency Oscillator Specifications

Table 5-9 Low-Frequency Oscillator Characteristics

5.15.4.4 Hibernation Low-Frequency Oscillator Specifications

Table 5-10 Hibernation External Oscillator (XOSC) Input Characteristics

Table 5-11 Hibernation Internal Low-Frequency Oscillator Clock Characteristics

5.15.4.5 Main Oscillator Specifications

Table 5-12 Main Oscillator Input Characteristics

Table 5-13 Crystal Parameters

5.15.4.6 Main Oscillator Specification WIth ADC

Table 5-14 System Clock Characteristics With ADC Operation

5.15.4.7 System Clock Characteristics With USB Operation

Table 5-15 System Clock Characteristics With USB Operation

5.15.5 Sleep Modes

Table 5-16 Wake From Sleep Characteristics

Table 5-17 Wake From Deep Sleep Characteristics

5.15.6 Hibernation Module

Table 5-18 Hibernation Module Battery Characteristics

Table 5-19 Hibernation Module Characteristics

Table 5-20 Hibernation Module Tamper I/O Characteristics

5.15.7 Flash Memory

Table 5-21 Flash Memory Characteristics

5.15.8 EEPROM

Table 5-22 EEPROM Characteristics

5.15.9 Input/Output Pin Characteristics

Table 5-23 Fast GPIO Module Characteristics

Table 5-24 Slow GPIO Module Characteristics

5.15.9.1 Types of I/O Pins and ESD Protection

5.15.9.1.1 Hibernate WAKE pin

Table 5-25 Pad Voltage and Current Characteristics for Hibernate WAKE Pin

5.15.9.1.2 Nonpower I/O Pins

Table 5-26 Nonpower I/O Pad Voltage and Current Characteristics

5.15.10 External Peripheral Interface (EPI)

Table 5-27 EPI Interface Load Conditions

Table 5-28 EPI SDRAM Characteristics

Table 5-29 EPI SDRAM Interface Characteristics

Table 5-30 EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics

Table 5-31 EPI General-Purpose Interface Characteristics

Table 5-32 EPI PSRAM Interface Characteristics

5.15.11 Analog-to-Digital Converter (ADC)

Table 5-33 Electrical Characteristics for ADC at 1 Msps

Table 5-34 Electrical Characteristics for ADC at 2 Msps

5.15.12 Synchronous Serial Interface (SSI)

Table 5-35 SSI Characteristics

5.15.2.1.1 V_DDA Levels

5.15.2.1.2 V_DD Levels

5.15.2.1.3 V_DDC Levels

5.15.2.1.4 V_DD Glitch Response

5.15.2.1.5 V_DD Droop Response

Table 5-7 Actual PLL Frequency⁽¹⁾

Table 5-36 Bi- and Quad-SSI Characteristics⁽¹⁾

5.15.13 Inter-Integrated Circuit (I²C) Interface

Table 5-37 I²C Characteristics

Table 5-39 MOSC 25-MHz Crystal Specification⁽¹⁾

Table 5-40 MOSC Single-Ended 25-MHz Oscillator Specification ⁽¹⁾